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4/29/2020

Godson 3A2000 / 3B2000 Processor User Manual

111

138

Page 143

Godson 3A2000 / 3B2000 Processor User Manual Part 1

CORE1_AWMASK0

0x3ff01908

RW

CORE1 AXI interface AW trigger enable 0 is set, the highest bit is AW channel trigger enable

The trigger condition is

(AW_IN & AWMASK) == (AWCOND & AWMASK)

CORE1_AWCOND1

0x3ff01910

RW

The trigger condition of AW must be satisfied by both COND0 and COND1

CORE1_AWMASK1

0x3ff01918

RW

CORE1_ARCOND0

0x3ff01920

RW

CORE1's AXI interface AR trigger condition, similar to AW

CORE1_ARMASK0

0x3ff01928

RW

CORE1_ARCOND1

0x3ff01930

RW

CORE1_ARMASK1

0x3ff01938

RW

CORE1_WCOND0

0x3ff01940

RW

CORE1's AXI interface W trigger condition, similar to AW

CORE1_WMASK0

0x3ff01948

RW

CORE1_WCOND1

0x3ff01950

RW

CORE1_WMASK1

0x3ff01958

RW

CORE1_WCOND2

0x3ff01960

RW

CORE1_WMASK2

0x3ff01968

RW

CORE1_BCOND0

0x3ff01970

RW

CORE1's AXI interface B trigger condition, similar to AW

CORE1_BMASK0

0x3ff01978

RW

CORE1_RCOND0

0x3ff01980

RW

CORE1's AXI interface R trigger condition, similar to AW

CORE1_RMASK0

0x3ff01988

RW

139

Page 144

Godson 3A2000 / 3B2000 Processor User Manual Part 1

CORE1_RCOND1

0x3ff01990

RW

CORE1_RMASK1

0x3ff01998

RW

CORE1_RCOND2

0x3ff019a0

RW

CORE1_RMASK2

0x3ff019a8

RW

TUD1_CONF0

0x3ff019e0

RW

TUD1 configuration register 0

[47: 0]: count_target

[55:48]: monitor_enable

TUD0 configuration register 1

[2: 0]: DCDL_sel_signal

Содержание 3A2000

Страница 1: ...Manual 1 Page 1 Loongson 3A2000 3B2000 processor User Manual volume One Multi core processor architecture register description and system software programming guide V1 7 2017 Nian 02 Yue Loongson Zhon...

Страница 2: ...ration Limited Address Building 2 Longxin Industrial Park Zhongguancun Environmental Protection Technology Demonstration Park Haidian District Beijing Building No 2 Loongson Industrial Park Zhongguanc...

Страница 3: ...d a section of software and hardware changes 3 2015 07 17 V1 2 Supplemental register description 4 2016 02 23 V1 3 Fix some register description errors modify software and hardware modification instru...

Страница 4: ...escription of control pins 16 2 3 Cache consistency 18 2 4 Physical address space distribution at the node level of the system 18 2 5 Address Routing Distribution and Configuration 19 2 6 Chip Configu...

Страница 5: ...62 10 4 2 Internal window configuration of HyperTransport controller 63 10 5 Configuration Register 64 10 5 1 Bridge Control 66 10 5 2 Capability Registers 66 10 5 3 User defined register 69 10 5 4 R...

Страница 6: ...uration space 96 10 7 HyperTransport bus frequency software configuration method 97 10 8 HyperTransport multiprocessor support 98 11 Low speed IO controller configuration 100 11 1 PCI Controller 100 1...

Страница 7: ...ongson No 3 system structure 11 Figure 1 2 Loongson No 3 node structure 12 Figure 1 3 Godson 3A2000 chip structure 13 Figure 3 1 GS464e structure diagram 31 Figure 7 1 Loongson 3A2000 processor interr...

Страница 8: ...and Processor Core Software Frequency Multiplication Setting Register Physical Address 0x1fe001b0 27 Table 2 14 Chip memory and HT clock software frequency multiplication setting register physical add...

Страница 9: ...ID Link Freq Link Error Link Freq Cap Registers 68 Table 10 12 Definition of Feature Capability Register 69 Table 10 13 MISC register definition 69 Table 10 14 Receive Diagnostic Register 70 Table 10...

Страница 10: ...Access 82 Table 10 49 HT Bus POST Address Window 1 Base Address Internal Access 82 Table 10 50 HT Bus Prefetchable Address Window 0 Enable Internal Access 83 Table 10 51 HT Bus Prefetchable Address W...

Страница 11: ...able 10 78 Training 3 Count Register 93 Table 10 79 Software Frequency Configuration Register 94 Table 10 80 PHY Configuration Register 95 Table 10 81 Link Initialization Debug Register 96 Table 10 82...

Страница 12: ...nect architecture design integrating multiple high end on a single chip Performance processor core and a large number of level 2 caches and also realize the interconnection of multiple chips through h...

Страница 13: ...four pairs of Master Slave Other nodes or IO nodes EM ES SM SS WM WS NM NS in the figure The X2 crossbar is connected to four shared caches through four Master ports and one is connected to at least o...

Страница 14: ...emory Controller Low end I O Controller Enhanced HT3 0 Controller CORE0 16B 16B CORE1 16B 16B CORE2 16B 16B CORE3 16B 16B 16B 16B 2B 2B Enhanced HT3 0 Controller 2B 2B 16B 16B 16B 16B 16B 16B 16B 16B...

Страница 15: ...de chip In order to ensure longer term stable and reliable operation and to be able to adapt to more demanding environmental temperature requirements the chip Reliability screening was conducted to el...

Страница 16: ...on model Large scale multi chip expansion interconnection through dedicated expansion bridges forming a large scale non uniform Uniform access to multi processor systems CC NUMA 2 2 Description of con...

Страница 17: ...signal effect CLKSEL 9 5 5 b11111 means MEM clock directly uses memclk 5 b01111 indicates that the MEM clock is set by software For the setting method see 2 6 Description In other cases the MEM clock...

Страница 18: ...s Table 2 2 Node level system global address distribution Chip node number NODEID Address 47 44 bits starting address End address 0 0 0x0000_0000_0000 0x0FFF_FFFF_FFFF 1 1 0x1000_0000_0000 0x1FFF_FFFF...

Страница 19: ...ort has 8 address windows which can be completed Target routing in 8 address windows Each address window consists of three 64 bit registers BASE MASK and MMAP BASE is aligned in K bytes MASK adopts a...

Страница 20: ...b8 CORE0_WIN7_MMAP 0x3ff0_21b8 CORE1_WIN7_MMAP 0x3ff0_2200 CORE2_WIN0_BASE 0x3ff0_2300 CORE3_WIN0_BASE 0x3ff0_2208 CORE2_WIN1_BASE 0x3ff0_2308 CORE3_WIN1_BASE 0x3ff0_2210 CORE2_WIN2_BASE 0x3ff0_2310 C...

Страница 21: ...N0_MMAP 0x3ff0_2688 HT0_WIN1_MMAP 0x3ff0_2788 HT1_WIN1_MMAP 0x3ff0_2690 HT0_WIN2_MMAP 0x3ff0_2790 HT1_WIN2_MMAP 0x3ff0_2698 HT0_WIN3_MMAP 0x3ff0_2798 HT1_WIN3_MMAP 0x3ff0_26a0 HT0_WIN4_MMAP 0x3ff0_27a...

Страница 22: ...ress at the first level cache of the processor resulting in incorrect maintenance of Cache consistency error Window hit formula IN_ADDR MASK BASE New address conversion formula OUT_ADDR IN_ADDR MASK M...

Страница 23: ...indow 4 base address 0x0 3ff0 0128 PCI_WIN5_BASE PCI window 5 base address 0x0 3ff0 0130 PCI_WIN6_BASE PCI window 6 base address 0x0 3ff0 0138 PCI_WIN7_BASE PCI window 7 base address 0x0 3ff0 0140 PCI...

Страница 24: ...ample in Loongson 3A2000 provide A mechanism to read and write the configuration of the chip 25 Page 30 Godson 3A2000 3B2000 Processor User Manual Part 1 Table 2 11 Chip Configuration Register Physica...

Страница 25: ...ck DIV_LOOPC DIV_OUT For the configuration method of HT CLOCK is special please refer to the specific configuration method in Section 10 5 28 In software control mode the default corresponding clock f...

Страница 26: ...0x1 23 14 MEM_PLL_DIV_LOOPC RW 0x41 MEM PLL input parameters 29 24 MEM_PLL_DIV_OUT RW 0x0 MEM PLL input parameters 32 SEL_HT0_PLL RW 0x0 HT0 non software bypass PLL 33 SOFT_SET_HT0_PLL RW 0x0 Allow s...

Страница 27: ...used as basic processor cores to form on chip multi core systems for server and high performance applications use Multiple GS464 cores and shared Cache modules in Loongson 3A2000 form one through AXI...

Страница 28: ...64e is shown in the figure below For more detailed introduction please refer to the GS464e user manual and MIPS64 user manual 30 Page 35 Godson 3A2000 3B2000 Processor User Manual Part 1 ITLB 64KB ICa...

Страница 29: ...er consumption Cache TAG The directory and data can be accessed separately The shared Cache status bit and w bit are stored with the TAG and the TAG is stored in the TAG RAM In the directory is stored...

Страница 30: ...08 47 0 No 1 lock window lock address Slock1_mask 0x3ff00248 47 0 No 1 lock window mask Slock2_valid 0x3ff00210 63 63 Lock window 2 valid bits Slock2_addr 0x3ff00210 47 0 No 2 lock window lock address...

Страница 31: ...the SCache The source matrix involved in transposing or moving may be a small matrix located in a large matrix so its matrix address It may not be completely continuous There will be gaps between the...

Страница 32: ...ontrol bit When arcache is 4 hf it must be set to 4 hc It is meaningless when arcache is other value 11 8 Arcache read command internal control bit When it is 4 hf the cache path is used and when it i...

Страница 33: ...t cleared 0 MailBox0 RW Cache register used to transfer parameters at startup according to 64 or 32 bit Uncache access MailBox01 RW Cache register used to transfer parameters at startup according to 6...

Страница 34: ...01228 RW IPI_MailBox1 register of processor core 2 Core2_ MailBox2 0x3ff01230 W IPI_MailBox2 register of processor core 2 Core2_ MailBox3 0x3ff01238 W IPI_MailBox3 register of processor core 2 Table 6...

Страница 35: ...or User Manual Part 1 7 I O interrupt Loongson 3A2000 chip supports up to 32 interrupt sources which are managed in a unified manner as shown in Figure 7 1 below any An IO interrupt source can be conf...

Страница 36: ...tenclr register is cleared Inten register reads the current interrupt Enabled situation The interrupt signal in the form of pulse such as PCI_SERR is selected by the Intedge configuration register wri...

Страница 37: ...f processor 3 41 Page 46 Godson 3A2000 3B2000 Processor User Manual Part 1 Table 7 3 Interrupt Routing Register Description Bit field Explanation 3 0 Routed processor core vector number 7 4 Routed pro...

Страница 38: ...preset temperature interruptions below the preset temperature and high temperature Automatic frequency reduction function 8 2 High and low temperature interrupt trigger For the high and low temperatur...

Страница 39: ...ow temperature interrupt enable 2 43 42 Lo_Sel2 Select the temperature sensor input source for low temperature interrupt 2 55 48 Lo_gate3 Low temperature threshold 3 below this temperature will genera...

Страница 40: ...er Manual Part 1 9 DDR2 3 SDRAM controller configuration The design of the integrated memory controller inside Loongson No 3 processor complies with the industry standard of DDR2 3 SDRAM JESD79 2 And...

Страница 41: ...E_n are composed of three signals For read operations RAS_n 1 CAS_n 0 and WE_n 1 46 Page 51 Godson 3A2000 3B2000 Processor User Manual Part 1 Figure 9 1 DDR2 SDRAM read operation protocol In the figur...

Страница 42: ...delay_3 Rddqs_lt_half_3 Wrdqs_lt_half_3 Wrdq_lt_half_3 0x088 Rd_oe_end_3 Rd_oe_begin_3 Rd_stop_edge_3 Rd_start_edge_3 Dqs_oe_end_3 Dqs_oe_begin_3 Dqs_stop_edge_3 Dqs_start_edge_3 0x090 Enzi_end_3 Enzi...

Страница 43: ...D Mrs_req WR 0x1A0 Mr_3_cs_0 Mr_2_cs_0 Mr_1_cs_0 Mr_0_cs_0 0x1A8 Mr_3_cs_1 Mr_2_cs_1 Mr_1_cs_1 Mr_0_cs_1 0x1B0 Mr_3_cs_2 Mr_2_cs_2 Mr_1_cs_2 Mr_0_cs_2 0x1B8 Mr_3_cs_3 Mr_2_cs_3 Mr_1_cs_3 Mr_0_cs_3 0x1...

Страница 44: ...tial operation The initialization operation is started when the software writes 1 to the register Init_start 0x018 Set Init_start Before the signal all other registers must be set to the correct value...

Страница 45: ...rnal reset POWER Software enableDLL lock Particle RESETn 2 Reverse mode reset_ctrl 1 0 2 b10 In this mode the reset signal pin is in memory In actual control the effective level is opposite to the gen...

Страница 46: ...e memory controller Operation Usually it includes Write Leveling Read Leveling and Gate Leveling In this controller Among them only Write Leveling and Gate Leveling are implemented Read Leveling is no...

Страница 47: ...ATA and tRDDATA by 1 15 Set Lvl_mode 0x180 to 2 b00 to exit Write Leveling mode 9 5 3 2 Gate Leveling Gate Leveling is used to configure the timing of the sampling and reading DQS window in the contro...

Страница 48: ...follows 1 Set the registers Cs_mrs 0x168 and Mr _cs 0x190 0x1B8 to the correct values 2 Set Command_mode 0x190 to 1 to make the controller enter the command sending mode 3 Sampling Status_cmd 0x190 if...

Страница 49: ...is officially started So far since the loop test has started the software needs to constantly check whether there is an error The specific operations are as follows 6 Sampling register Lpbk_error 0x2...

Страница 50: ...0E00_0000_0000 0x0FFF_FFFF_FFFF can be configured by software to support inter chip cache consistency For maintenance see section 10 8 The HyperTransport controller supports up to 16 bit bidirectional...

Страница 51: ...led by the opposite device HT0_Lo_Rstn Bus Rstn HyperTransport bus Rstn signal When HT0_Lo_Mode is 1 it is controlled by HT0_Lo When HT0_Lo_Mode is 0 it is controlled by the opposite device HT0_Lo_Ldt...

Страница 52: ...uency 200MHz and the smallest width 8bit and try to initiate a bus initialization handshake initialization Whether it is in the completed state can be read from the register Init Complete see Section...

Страница 53: ...RespCoherent Read response extension 111001 NPC RdCoherent Read command extension 111011 NPC RdAddr Read address extension 111111 Sync Error Will only forward 10 3 HyperTransport interrupt support Hy...

Страница 54: ...configuration space 0xFD_FC00_0000 0xFD_FDFF_FFFF 32 Mbytes I O space 0xFD_FE00_0000 0xFD_FFFF_FFFF 32 Mbytes HT bus configuration space 0xFE_0000_0000 0xFF_FFFF_FFFF 8 Gbytes Keep 10 4 2 Internal wi...

Страница 55: ...er First the access and storage of configuration registers used to control various behaviors of the HT controller are in this module The access offset address is 0xFD_FB00_0000 to 0xFD_FBFF_FFFF on th...

Страница 56: ...T bus Uncache address window 3 enable external access 0x174 HT bus Uncache address window 3 base address external access 0x158 P2P address window configuration register HT bus P2P address window 0 ena...

Страница 57: ...0x0 Whether R W prohibits register access from HT bus twenty three Reserved 1 0x0 Keep 22 18 Unit ID 5 0x0 R W In HOST mode can be used to record the number of IDs used In SLAVE mode record your own U...

Страница 58: ...ed by bit 0 6 End of Chain 0 0x0 R HT bus end 5 Init Complete 1 0x0 R Whether the HT bus initialization is completed 4 Link Fail 1 0x0 R Indicates connection failure 3 2 Reserved 2 0x0 Keep 1 CRC Floo...

Страница 59: ...s into LDT DISCONNECT mode The correct method is 0 1 29 Ldt Req Gen 1 0x0 R W Wake up HT bus from LDT DISCONNECT set LDT_REQ_n The correct way is to set 0 first and then set 0 0 1 In addition direct r...

Страница 60: ...ic register Offset 0x54 Reset value 0x00000000 Name Receive diagnostic register Table 10 14 Receive Diagnostic Register Bit field Bit field name Bit width reset value Visit description 0 Sample_en 1 0...

Страница 61: ...eceive address window is the address received on the HT bus The HT address falling within the P2P window will be regarded as P2P 71 Page 76 Godson 3A2000 3B2000 Processor User Manual Part 1 The comman...

Страница 62: ...w 2 enable external access Table 10 21 HT Bus Receive Address Window 2 Enable External Access Register Definition Bit field Bit field name Bit width reset value Visit description 31 ht_rx_image2_en 1...

Страница 63: ...h reset value Visit description 31 ht_rx_image4_en 1 0x0 R W HT bus receives address window 4 enable signal 30 ht_rx_image4_ trans_en 1 0x0 R W HT bus receives address window 4 map enable signal 29 0...

Страница 64: ...pt line 0 HT HI corresponds to interrupt line 4 1 5 9 13 253 corresponds to interrupt line 1 HT HI corresponds to interrupt line 5 2 6 10 14 254 corresponds to interrupt line 2 HT HI corresponds to in...

Страница 65: ...to interrupt line 2 HT HI Corresponding to interrupt line 6 Offset 0x94 76 Page 81 Godson 3A2000 3B2000 Processor User Manual Part 1 Reset value 0x00000000 Name HT Bus Interrupt Vector Register 191 1...

Страница 66: ...esponds to interrupt line 3 HT HI corresponds to interrupt line 7 ht_int_stripe_4 0 4 8 12 252 corresponds to interrupt line 0 HT HI corresponds to interrupt line 4 1 5 9 13 253 corresponds to interru...

Страница 67: ...HT Bus Interrupt Enable Register Definition 5 Bit field Bit field name Bit width reset value Visit description 31 0 Interrupt_mask 159 128 32 0x0 R W HT bus interrupt enable register 159 128 Correspo...

Страница 68: ...ity ID 8 0x08 R Hypertransport Capablity ID Offset 0xc4 Reset value 0x00000000 Name Dataport Table 10 43 Dataport register definition Bit field Bit field name Bit width reset value Visit description 3...

Страница 69: ...address window 0 the translated address 39 24 Offset 0xd4 Reset value 0x00000000 Name HT bus POST address window 0 base address internal access 81 Page 86 Godson 3A2000 3B2000 Processor User Manual Pa...

Страница 70: ...HT bus can prefetch address window 0 enable signal 30 23 Reserved 15 0x0 Keep 15 0 ht_prefetch0_trans 39 24 16 0x0 R W HT bus can prefetch the address window 0 the translated address 39 24 Offset 0xe4...

Страница 71: ...window is mainly aimed at some CACHE hits operations that can increase the efficiency of storage such as video memory access Offset 0xf0 Reset value 0x00000000 Name HT bus Uncache address window 0 ena...

Страница 72: ...lue 0x00000000 Name HT bus Uncache address window 2 enable internal access Table 10 58 HT Bus Uncache Address Window 2 Enable Internal Access Bit field Bit field name Bit width reset value Visit descr...

Страница 73: ...nd is forwarded back to the bus which has the highest priority relative to the normal receive window and Uncache window Offset 0x158 Reset value 0x00000000 Name HT bus P2P address window 0 enable exte...

Страница 74: ...uffer size register is used to observe the number of buffers available for each command channel at the sending end Offset 0x100 Reset value 0x00000000 Name Command send buffer size register Table 10 6...

Страница 75: ...decrease the number of PC channel data buffers at the sending end When tx_neg is 0 add PC_DATA_txadj When tx_neg is 1 reduce PC_DATA_txadj 1 15 12 B_CMD_txadj 4 0x0 R W Number of increase and decreas...

Страница 76: ...enable error retransmission in HyerTransport 3 0 mode configure the maximum number of Short Retry display Whether the Retry counter rolls over Offset 0x118 Reset value 0x00000000 Name Error Retry Con...

Страница 77: ...ling 13 10 Reserved 4 0x0 R Keep 8 7 Receiver LS select 2 0x0 R W The receiver is in Disconnected or Inactive state Link status 2 b00 LS1 91 Page 96 Godson 3A2000 3B2000 Processor User Manual Part 1 2...

Страница 78: ...ounting register Table 10 76 Training 1 count register Bit field Bit field name Bit width reset value Visit description 31 0 T1 time 32 0x4fffff R W Training 1 Count register 10 5 26 Training 2 count...

Страница 79: ...MHz div_loop div_refc HT_CORE_CLK 100MHz div_loop div_refc core_div The time to wait for the PLL to relock is about 30us by default when the system clk is 33M Write a custom upper limit of wait count...

Страница 80: ...0 PLL clock 1 b1 external clock source 27 26 Rx_ctle_bitc 2 0x0 R W PAD EQD high frequency gain 25 24 Rx_ctle_bitr 2 0x3 R W PAD EQD low frequency gain 23 22 Rx_ctle_bitlim 2 0x0 R W PAD EQD compensat...

Страница 81: ...as the PCI protocol Since the access to the configuration space is directly The underlying protocol is related and the specific access details are slightly different As listed in Table 10 5 the addres...

Страница 82: ...n the reset signal of HT cannot be connected together At this time it needs to be prevented by software control HT LO affects HT HI when switching the PLL frequency The most direct way is to first set...

Страница 83: ...he two processors Two chips The numbers are 00 and 01 respectively From the routing algorithm we can know that when two chips access each other they are connected to 8 bit HT bus at the same time As f...

Страница 84: ...04 Class Code Revision ID 08 BIST Header Type Latency Timer CacheLine Size 0C Base Address Register 0 10 Base Address Register 1 14 Base Address Register 2 18 Base Address Register 3 1C Base Address...

Страница 85: ...22 20 tar_subseq_timeout Read and write 000 target subsequent delay timeout 000 8 cycles Other Not supported 19 16 tar_init_timeout Read and write 0000 target initial delay timeout In PCI mode 0 16 c...

Страница 86: ...ar 11 ctrl_parity_error Read and write 0 Target master address parity error write 1 clear 10 0 Reserved REG_50 31 0 mas_pending_seq Read and write 0 Vector of unprocessed request number of master The...

Страница 87: ...t 6 0 The rotation based arbitration algorithm provides two levels and the second level as a whole is scheduled as a member of the first level Dangduo When a device applies for the bus at the same tim...

Страница 88: ...or Firmware Memory access type The type of access issued at system startup is controlled by the LPC_ROM_INTEL pin LPC Firmware Memory access is issued when the LPC_ROM_INTEL pin is pulled up and issu...

Страница 89: ...interrupt system with arbitration Only work in FIFO mode Compatible with NS16550A in register and function The chip integrates two UART interfaces the function registers are exactly the same but the a...

Страница 90: ...Bit 3 Bit 2 Bit 1 Priority interrupt type Interrupt source Interrupt reset control 0 1 1 1st Receive line status Parity overflow or frame error or hit Interrupt Read LSR 0 1 0 2nd Received valid numb...

Страница 91: ...ol bit 1 At this time the output of the serial port is set to 0 interrupted state 0 normal operation 5 spb 1 RW Specify parity 0 no parity bit specified 1 transmission and check parity if LCR 4 bit is...

Страница 92: ...1 the output shift register is directly connected to the input shift register The other connections are as follows DTR DSR RTS CTS Out1 RI Out2 DCD 3 OUT2 1 W Connect to DCD input in loopback mode 2...

Страница 93: ...rror indicates bit 1 The current received data has a parity error 0 no parity error 1 OE 1 R Data overflow indication bit 1 There is data overflow 0 no overflow 0 DR 1 R Receive data valid representat...

Страница 94: ...of the divider latch 11 4 SPI controller The SPI controller has the following features Full duplex synchronous serial data transmission Supports up to 4 variable length byte transmission Main mode su...

Страница 95: ...ter SPSR Chinese name Status Register Register bit width 7 0 Offset 0x01 Reset value 0x05 Bit field Bit field name Bit width access description 7 spif 1 RW Interrupt flag bit 1 indicates that there is...

Страница 96: ...egister bit width 7 0 Offset 0x04 Reset value 0x21 Bit field Bit field name Bit width access description 7 4 clk_div 4 RW Clock frequency division number selection frequency division coefficient is th...

Страница 97: ...y Clock period T calculation 00 1T 01 2T 10 4T 11 8T 116 Page 121 Godson 3A2000 3B2000 Processor User Manual Part 1 11 5 IO controller configuration The configuration register is mainly used to config...

Страница 98: ..._Sel_L PCI window 0 controls the lower 32 bits 117 Page 122 Godson 3A2000 3B2000 Processor User Manual Part 1 54 PCI_Hit0_Sel_H PCI window 0 controls the upper 32 bits 58 PCI_Hit1_Sel_L PCI Window 1 c...

Страница 99: ...write 31 17 Reserved Read only 0 CR1C GPIO_Data 15 0 gpio_out Read write 0 GPIO output data 31 16 gpio_in Read write 0 GPIO input data CR20 GPIO_EN 15 0 gpio_en Read and write FFFF High is input low...

Страница 100: ...1 bit can be obtained after the bus To occupy the bus with continuous requests 31 13 Reserved Read only 0 CR6C PXArb_Status 7 0 broken_master Read only 0 Damaged master device cleared when changing th...

Страница 101: ...3ff00078 RW Mask of CPU window 7 0x0 Page 126 Godson 3A2000 3B2000 Processor User Manual Part 1 CPU_WIN0_MMAP 0x3ff00080 RW New base address of CPU window 0 0xf0 CPU_WIN1_MMAP 0x3ff00088 RW New base a...

Страница 102: ...ck address of lock window 0 63 valid 47 0 addr 0x0 Slock1_addr 0x3ff00208 RW Lock address of lock window 1 63 valid 47 0 addr 0x0 Slock2_addr 0x3ff00210 RW Lock address of lock window 2 63 valid 47 0...

Страница 103: ...W 0x0 MTX1_DST_ROW_STRIDE 0x3ff00728 RW 0x0 MTX1_TRANS_CTRL 0x3ff00730 RW 0x0 SCache0_perfctrl0 0x3ff00800 RW SCache0_perfcnt0 0x3ff00808 RO SCache0_perfctrl1 0x3ff00810 RW SCache0_perfcnt1 0x3ff00818...

Страница 104: ...0x3ff0100c WO IPI_Clear register of processor core 0 Core0_MailBox0 0x3ff01020 RW IPI_MailBox0 register of processor core 0 0x0 Core0_MailBox1 0x3ff01028 RW IPI_MailBox1 register of processor core 0...

Страница 105: ...r of processor core 3 Core3_IPI_Clear 0x3ff0130c WO IPI_Clear register of processor core 3 Core3_MailBox0 0x3ff01320 RW IPI_MailBox0 register of processor core 3 0x0 128 Page 133 Godson 3A2000 3B2000...

Страница 106: ...re sensor input source for high temperature interrupt 3 130 Page 135 Godson 3A2000 3B2000 Processor User Manual Part 1 Thsens_int_ctrl_Lo 0x3ff01468 RW Temperature sensor low temperature interrupt con...

Страница 107: ...uced 40 40 Scale_en2 High temperature frequency reduction enable 2 43 42 Scale_Sel2 Select the temperature sensor input source for high temperature down conversion 2 46 44 Scale_freq2 frequency divisi...

Страница 108: ...ger enable 0 is set the highest bit is AW channel trigger enable 49 0 awmask 62 awdata_en trigger is allowed only when the wdata trigger condition of the same wid is met at the same time 63 awchannel_...

Страница 109: ...0x3ff01830 RW 47 0 araddr CORE0_ARMASK1 0x3ff01838 RW 135 Page 140 Godson 3A2000 3B2000 Processor User Manual Part 1 CORE0_WCOND0 0x3ff01840 RW CORE0 s AXI interface W trigger condition similar to AW...

Страница 110: ...r enable 0 setting the highest bit is the R channel trigger enable 27 0 rmask 63 rchannel_en CORE0_RCOND1 0x3ff01890 RW CORE0_RMASK1 0x3ff01898 RW CORE0_RCOND2 0x3ff018a0 RW CORE0_RMASK2 0x3ff018a8 RW...

Страница 111: ...K1 0x3ff01938 RW CORE1_WCOND0 0x3ff01940 RW CORE1 s AXI interface W trigger condition similar to AW CORE1_WMASK0 0x3ff01948 RW CORE1_WCOND1 0x3ff01950 RW CORE1_WMASK1 0x3ff01958 RW CORE1_WCOND2 0x3ff0...

Страница 112: ...WCOND1 0x3ff01a10 RW The trigger condition of AW must be satisfied by both COND0 and COND1 CORE2_AWMASK1 0x3ff01a18 RW CORE2_ARCOND0 0x3ff01a20 RW CORE2 s AXI interface AR trigger condition similar to...

Страница 113: ...0 DCDL_sel_signal 5 3 DCDL_sel_clock 9 6 signal_sel 13 10 clok_sel 20 14 reading_sel 21 counter_clock_sel 22 sticky 23 reset_g 24 stop 25 start 26 cg_en TUD2_RESULT 0x3ff01af0 R TUD2 result register C...

Страница 114: ...face B trigger condition similar to AW CORE3_BMASK0 0x3ff01b78 RW CORE3_RCOND0 0x3ff01b80 RW CORE3 s AXI interface R trigger condition similar to AW CORE3_RMASK0 0x3ff01b88 RW CORE3_RCOND1 0x3ff01b90...

Страница 115: ...9 clock_sel 18 12 reading_sel 19 counter_clock_sel 20 sticky 21 reset_g 22 stop 23 start 24 cg_en TUD4_RESULT 0x3ff01cf0 R TUD4 result register TUD5_CONF0 0x3ff01de0 RW TUD5 configuration register 0...

Страница 116: ...8 RW HT0_WCOND0 0x3ff01e40 RW HT0 s AXI interface W trigger condition similar to AW HT0_WMASK0 0x3ff01e48 RW HT0_WCOND1 0x3ff01e50 RW HT0_WMASK1 0x3ff01e58 RW HT0_WCOND2 0x3ff01e60 RW HT0_WMASK2 0x3ff...

Страница 117: ...3ff02000 RW First level crossbar address window 0x0 CORE0_WIN1_BASE 0x3ff02008 RW First level crossbar address window 0x0 CORE0_WIN2_BASE 0x3ff02010 RW First level crossbar address window 0x0 CORE0_WI...

Страница 118: ...SK 0x3ff02140 RW First level crossbar address window 0x0 CORE1_WIN1_MASK 0x3ff02148 RW First level crossbar address window 0x0 151 Page 156 Godson 3A2000 3B2000 Processor User Manual Part 1 CORE1_WIN2...

Страница 119: ...sbar address window 0x0 CORE2_WIN3_MMAP 0x3ff02298 RW First level crossbar address window 0x0 CORE2_WIN4_MMAP 0x3ff022a0 RW First level crossbar address window 0x0 CORE2_WIN5_MMAP 0x3ff022a8 RW First...

Страница 120: ...el crossbar address window 0x0 EAST_WIN2_BASE 0x3ff02410 RW First level crossbar address window 0x0 EAST_WIN3_BASE 0x3ff02418 RW First level crossbar address window 0x0 EAST_WIN4_BASE 0x3ff02420 RW Fi...

Страница 121: ...2548 RW First level crossbar address window 0x0 SOUTH_WIN2_MASK 0x3ff02550 RW First level crossbar address window 0x0 SOUTH_WIN3_MASK 0x3ff02558 RW First level crossbar address window 0x0 SOUTH_WIN4_M...

Страница 122: ...RW First level crossbar address window 0x0 WEST_WIN6_MMAP 0x3ff026b0 RW First level crossbar address window 0x0 158 Page 163 Godson 3A2000 3B2000 Processor User Manual Part 1 WEST_WIN7_MMAP 0x3ff026b...

Страница 123: ...13 Software and Hardware Design Guidelines Loongson 3A2000 processor pins are downward compatible with Loongson 3A1000 processor but the corresponding software and hardware need to be carried out Conf...

Страница 124: ...he memory frequency 9 CLKSEL 4 0 needs to be set to 5 b01111 use PMON to set the processor core frequency 10 For the 3A2H motherboard you need to remove the pull up resistors on HT0 1_powerok and HT0...

Страница 125: ...zzer to ensure that the user can hear the buzzer 2 Add support to shut down the defective core clock 13 4 Guidelines for kernel changes The modifications required in the kernel include 1 Modify the Ca...

Страница 126: ...ally maintains consistency Modifications that can also be used to improve performance are 1 Increase support for FTLB 2 Add support for TLB fast refill 3 Add wait instruction support 4 Add prefetch in...

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