LTM9004
18
9004fa
For more information
www.linear.com/LTM9004
Enable Interface
The enable voltage necessary to turn on the mixer is 2V.
To disable or turn off the mixer, this voltage should be
below 1V. If this pin is not connected, the mixer is disabled.
However, it is not recommended that the pin be left floating
for normal operation.
The AMP1ENABLE and AMP2ENABLE pins are CMOS logic
inputs with internal pull-up resistors. If the pin is driven
low, the amplifier powers down with Hi-Z outputs. If the
pin is left unconnected or driven high, the part is in normal
active operation. Some care should be taken to control
leakage currents at this pin to prevent inadvertently putting
it into shutdown. The turn-on and turn-off time between
the shutdown and active states are typically less than 1μs.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting ADCSHDNx to GND results
in normal operation. Connecting ADCSHDNx to V
DD
and
OE
x to V
DD
results in sleep mode, which powers down
all circuitry including the reference and the ADC typically
dissipates 1mW. When exiting sleep mode, it will take
milliseconds for the output data to become valid because
the reference capacitors have to recharge and stabilize.
Connecting ADCSHDNx to V
DD
and
OE
x to GND results
in nap mode and the ADC typically dissipates 30mW. In
nap mode, the on-chip reference circuit is kept on, so that
recovery from nap mode is faster than that from sleep
mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels I and Q have independent ADCSHDN pins
(ADCSHDNI, ADCSHDNQ.) I-Channel is controlled by
ADCSHDNI and
OEI
, and Q-Channel is controlled by
ADCSHDNQ and
OEQ
. The nap, sleep and output enable
modes of the two channels are completely independent,
so it is possible to have one channel operating while the
other channel is in nap or sleep mode.
Note that ADCSHDN has the opposite polarity as MIXEN-
ABLE, AMP1ENABLE and AMP2ENABLE. Normal operation
is achieved with a logic low level on the SHDN pins and a
high level disables the respective functions.
It is not recommended to enable or shut down individual
components separately. These pins are separated for test
purposes.
Driving the ADC Clock Inputs
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (Figure 7).
applicaTions inForMaTion
Figure 7. Sinusoidal Single-Ended CLK Driver
CLK
50Ω
0.1µF
0.1µF
4.7µF
1k
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
9004 F07
NC7SVU04
LTM9004
The noise performance of the ADC can depend on the clock
signal quality as much as on the analog input. Any noise
present on the CLK signal will result in additional aperture
jitter that will be RMS summed with the inherent ADC
aperture jitter. In applications where jitter is critical, such
as when digitizing high input frequencies, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, filter the CLK signal to reduce wideband
noise and distortion products generated by the source.
It is recommended that CLKI and CLKQ are shorted to-
gether and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKI and CLKQ can be driven
by two different signals. If this time delay exceeds 1ns,
the performance of the part may degrade. CLKI and CLKQ
should not be driven by asynchronous signals.
