LTM9004
15
9004fa
For more information
www.linear.com/LTM9004
Broadband transformers are integrated at both the RF and
LO inputs to enable single-ended RF and LO interfaces.
In the high frequency band (1.5GHz to 2.7GHz), both RF
and LO ports are internally matched to 50Ω. No external
matching components are needed. For the lower frequency
bands (700MHz to 1.5GHz), a simple network with series
and/or shunt capacitors can be used as the impedance
matching network.
I-CHANNEL AND Q-CHANNEL PHASE RELATIONSHIP
The phase relationship between the I-channel output signal
and the Q-channel output signal is fixed. When the LO
input frequency is larger (or smaller) than the RF input
frequency, the Q-channel outputs (DQ0 to DQ13) lag (or
lead) the I-channel outputs (DI0 to DI13) by 90°.
DC OFFSET ADJUSTMENT
Each channel includes provision for adjustment of the DC
offset voltage presented at the input of the A/D converter.
There are two adjust terminals for each channel, so that
the common mode and differential mode DC offset may
be independently trimmed. These terminals are designed
to accept a source or sink current of up to 0.3mA. If the
currents through the two terminals are not equal, then a
differential DC offset will be created. If they are equal, then
the resulting DC offset will be common mode only. As an
example, sinking 0.1mA from one terminal and 0.11mA
from the other terminal will yield a differential DC offset
of approximately 5.9mV or 48LSB. A maximum DC offset
of approximately 178mV or 1457LSB can be imposed by
applying a 5V differential voltage to the adjust terminals.
AMPLIFIER OPERATION
Each channel of the LTM9004 consists of two stages of
DC-coupled, low noise and low distortion fully differential
op amps/ADC drivers. Each stage implements a 2-pole
active lowpass filter using a high speed, high performance
operational amplifier and precision passive components.
The cascade of two stages is designed to provide maximum
gain and phase flatness, along with adjacent channel and
blocker rejection. The lowpass response can be config-
ured for different cutoff frequencies within the range of
the amplifiers. LTM9004-AA, for example, implements a
lowpass filter designed for 1.92MHz.
ADC INPUT NETWORK
The passive network between the second amplifier output
stages and the ADC input stages provides a 1st order
topology configured for lowpass response.
CONVERTER OPERATION
The analog-to-digital converter (ADC) shown in Figure 1 is
a dual CMOS pipelined multistep converter. The converter
has six pipelined ADC stages; a sampled analog input will
result in a digitized value six cycles later (see the Timing
Diagrams section). The CLK inputs are single ended. The
ADC has two phases of operation, determined by the state
of the CLK input pins.
Each pipelined stage contains an ADC, a reconstruction
DAC and an interstage residue amplifier. In operation, the
ADC quantizes the input to the stage and the quantized
value is subtracted from the input by the DAC to produce a
residue. The residue is amplified and output by the residue
amplifier. Successive stages operate out of phase so that
when the odd stages are outputting their residue, the even
stages are acquiring that residue and visa versa.
When CLK is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors.
At the instant that CLK transitions from low to high, the
sampled input is held. While CLK is high, the held input
voltage is buffered by the S/H amplifier which drives the
first pipelined ADC stage. The first stage acquires the
output of the S/H during this high phase of CLK. When
CLK goes back low, the first stage produces its residue
which is acquired by the second stage. At the same time,
the input S/H goes back to acquiring the analog input.
When CLK goes back high, the second stage produces its
residue which is acquired by the third stage. An identical
process is repeated for the third, fourth and fifth stages,
resulting in a fifth stage residue that is sent to the sixth
stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
operaTion
