Linear Technology LTM9004, Руководство пользователя

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LTM9004
12
9004fa
For more information www.linear.com/LTM9004
pin FuncTions
Connecting ADCSHDNI to V
DD
and OEI to GND results in
nap mode with the outputs at high impedance. Connecting
ADCSHDNI to V
DD
and OEI to V
DD
results in sleep mode
with the outputs at high impedance.
SENSEQ (Pin H13), SENSEI (Pin E13): ADC Reference
Programming Pin. Tie to V
DD
for normal operation. An
external reference can be used, see ADC Reference section.
MODE (Pin J13): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight binary
output format and turns the clock duty cycle stabilizer off.
1/3 V
DD
selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 V
DD
selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. V
DD
selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
MUX (Pin D13): Digital Output Multiplexer Control. If MUX
= high, Q-channel comes out on DQ0 to DQ13; I-channel
comes out on DI0 to DI13. If MUX = low, the output busses
are swapped and Q-channel comes out on DI0 to DI13;
I-channel comes out on DQ0 to DQ13. To multiplex both
channels onto a single output bus, connect MUX, CLKQ
and CLKI together.
OEQ (Pin K13): Q-Channel Output Enable Pin. Refer to
ADCSHDNQ pin function.
OEI (Pin C13): I-Channel Output Enable Pin. Refer to
ADCSHDNI pin function.
Digital Outputs
CLKOUT (Pin E12):
ADC Data Ready Clock Output. Latch
data on the falling edge of CLKOUT. CLKOUT is derived
from CLKQ. Tie CLKQ to CLKI for simultaneous operation.
DI0 - DI13 (See Table for Pin Locations): I-Channel
(In-Phase) ADC Digital Outputs. DI13 is the MSB.
DQ0 - DQ13 (See Table for Pin Locations): Q-Channel
(Quadrature) ADC Digital Outputs. DQ13 is the MSB.
OF (Pin H12): Overflow/Underflow Output. High when an
overflow or underflow has occurred on either I-channel or
Q-channel.
Pin Configuration
A B C D E F G H J K L M
1 GND I
+
_ADJ I
–
_ADJ GND GND GND GND GND GND Q
+
_ADJ Q
–
_ADJ GND
2 GND GND GND GND RF GND GND V
CC1
GND GND GND GND
3 GND GND GND GND GND GND GND LO GND GND GND GND
4 GND GND GND GND MIX_EN GND GND GND GND GND GND GND
5 GND GND V
CC2
AMP1A_
EN
GND GND V
CC1
GND GND V
CC2
AMP1B_
EN
GND
6 GND GND GND GND GND GND GND GND GND GND GND GND
7 GND GND GND GND GND GND GND GND GND GND GND GND
8 GND GND V
CC2
GND GND GND GND GND GND V
CC2
GND GND
9 GND GND V
CC3
GND GND GND GND GND GND V
CC3
GND GND
10 GND GND AMP2A_
EN
GND GND GND GND GND GND GND AMP2B_
EN
GND
11 GND GND GND GND GND GND GND GND GND GND GND GND
12 GND GND V
CC3
SHDNI CLKOUT GND GND OF SHDNQ V
CC3
GND GND
13 DI3 DI0 OEI MUX SENSEI V
DD
V
DD
SENSEQ MODE OEQ DQ13 DQ10
14 DI8 DI4 DI1 V
DD
GND CLKI CLKQ GND V
DD
DQ12 DQ8 DQ6
15 DI7 DI6 DI2 GND GND GND GND GND GND DQ11 DQ4 DQ5
16 GND DI9 DI5 DI10 DI11 GND GND DQ1 DQ3 DQ9 DQ7 GND
17 GND GND OGND OV
DD
DI12 DI13 DQ0 DQ2 OV
DD
OGND GND GND
Top View of LGA Package (Looking Through Component)