SMA1
DATA
(8 bits)
When writing to the register: this is the value to be set in the register (i.e.
transmitted from the Master to the Slave).
When reading from the register: this is the value read in the register (i.e.
transmitted from the Slave to the Master).
Data bit structure:
bit
7
…
…
0
MSB
…
…
LSB
CRC
(4 bits)
CRC, namely Cyclic Redundancy Check, is the error checking field resulting from
a “Redundancy Check” calculation performed on the message contents. This is
intended to check whether transmission has been performed properly (inverted
output).
Polynomial: X
4
+X
1
+1 (binary: 10011)
Logic circuit:
6.4 Sensor mode
Sensor mode data (32 bits) consists of the following values: 24-bit position
value (
, nW) and CRC
checking (
, 6 bits).
Sensor data structure:
Start
DATA
Stop
31 … 8
7
6
5 … 0
WARNING
Multi-cycle-data bit (MCD) is not utilized, thus the Master must not require it!
MAN SMA1 E 2.9.odt
6 - BiSS B-mode interface
21 of 48
1st
stage
2nd
stage
3rd
stage
4th
stage
X
0
X
1
X
2
X
3
Input Data (starts from MSB)