6. BLOCK DIAGRAM
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Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
PACT
30
LGE Internal Use Only
8. AUDIO Block Diagram
AP30
V_I2S
M_I2S
MCLK 1_2
SDA
SCL
PDM_FRAME
GEN1_I2C1_SDA
GEN1_I2C1_SCL
DAP1
DAP2
AUDIO_MCLK1_2
I2C1_SDA
I2C1_SCL
MAX98089
(Audio Codec)
RCV
EARP
EARN
RCV_P
RCV_N
DAP (I2S) Port
I2S
INTERFACE
HFRP1
HFRN1
SPK_P
SPK_N
SPK
SUB_MIC
SMICN
SMICP
3.5
Φ
HSL
HSR
EAR_L
EAR_R
HMICP
HS_MIC
BT_PCM_SYNC
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_CLK
PCM_AUD_FSYNC
PCM_AUD_IN
PCM_AUD_OUT
PCM_AUD_CLK
SDIO_DATA_[0:3]
SDIO_CMD
SDIO_CLK
WLAN_SDIO_[0:3]
SDMMC1_DATA[0:3]
SDMMC1_CLK
SDMMC1_CMD
WLAN_CLK
WLAN_CMD
I2S
INTERFACE
DAP4
INTERFACE
DAP3_CLKX
DAP3_DR
DAP3_DX
DAP3_FSX
IPC_I2S_DIN
IPC_I2S_DOUT
IPC_I2S_CLK
IPC_I2S_SYNC
XMM6260
I2S2_CLK0
I2S2_TX
I2S2_RX
I2S2_WA0
I2S
INTERFACE
I2S
INTERFACE
CODEC
MAIN_MIC
MMICN
MMICP
BT / WiFi (BCM4330X)
VIBE_PWM
VIBE_EN
EN
PWM
ISA1000
VDP
VDD
VIBRATOR
DAP4_SYNC
DAP4_DOUT
DAP4_DIN
DAP4_CLK
AUDIO Block Diagram