6. BLOCK DIAGRAM
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Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
PACT
30
LGE Internal Use Only
Power on Switch(High Active)
AP30
(AP)
MAX77663
(AP PMIC)
4-4. System Power On/Off
PWRON
PWR_ON_SW
VDD_RTC
OUT_LDO4
+1V2_TPS_VRTC
VDD_CORE
SD1
+1V2_TPS_VCORE
AVDD_PLLS
OUT_LDO0
+1V2_TPS_VPLL
VDDIO_SYS
OUT_LDO3
+1V8_LDO3
32KHZ IN
32K_OUT
AP_32K_CLK_IN
AVDD_OSC
OUT_LDO6
Xtal_out
VDDIO_DDR
SD3
+1V2_TPS_VDDR
VDD_DDR_RX
OUT_LDO5
SYS_RESET_N
NRST_IO
AP_SYS_RESET_N
+1V8_TPS_AVDD_OSC
+2V85_TPS_VMEM
SYS_RESET_N
NRST_IO
VDD_RTC
OUT_LDO4
+1V2_TPS_VRTC
VDD_CORE
SD1
+1V2_TPS_VCORE
32KHZ IN
32K_OUT
AP_32K_CLK_IN
VDDIO_SYS
OUT_LDO3
+1V8_LDO3
AP_SYS_RESET_N
Power on sequence
Power off sequence
System Power On/Off
VDD_RTC
VDD_RTC
VDD_CORE
VDD_CORE
AVDD_PLLs
Vcore_ramp
Vcore_ramp
Tvboot
Tvboot
Tvboot
Tck32_to_reset
Tose_to_reset
Tccresrtup
Tccrehold
Tccrehold
Trails_to_reset
Vm_pin
Vm_pin
Vm_pin
Vm_pin
Tvrx
Tvboot
Tvboot
Tvboot
VDDIO_SYS
VDDIO_SYS
All other Tegra rails
CORE_PWR_REO and
CPU_PWR_REO
VDDIO_DDR
VDD_DDR_RX
VDD_CPU
SYS_RESET_N
SYS_RESET_N
Other Required Rails
32KHz Out
32KHz Out
AVDD_OSC
System Clock (Xtal_out)
1
1
2
4
2a
2b
2c
3
3
Timestamp 1 : both VDD_CORE and VDD_RTC are power and stable
Timestamp 2a : all of the rails required for boot are powered and atable
Timestamp 2b : System clock is oscillating within spec. When using the Tegra oscillator in oscillator mode, timestamp 2b is 10ms AVDD_OSC is power on
Timestamp 2c : the 32kHz oscillator has provided at least 4 clean rising and is oscillating within spec
Timestamp 3 : SYS_RESET_N is deasserted and Tegra processor’s boot ROM begins execution
Timestamp 1 : both VDD_CORE and VDD_RTC are powered and stable
Timestamp 2 : SYS_RESET_N is asseried (i.e falls below Vll.) All reguiators other than VDD_CORE and VDD_RTC can be turmed off.
Timestamp 3 : All Tegra power ralls other than VDD_CORE and VDD_RTC are below 200mV.
Timestamp 3 : SYS_RESET_N is de-asserted and Tegra’s boot ROM begins execution
Note : The Trgra processor drives CORE_PWR_REO and CPU_PWR_REO as programmed by soltware untill system-level hardware asserts SYS_RESET_N.
The assertion of SYS_RESET_N causes Tegra to tristate its CORE_PWR_REO and CPU_PWR_REO buffers. As a resuit. the state of the wires will
depend on system-level hardware (e.g pull-ups/pull-downs)