LG KG920, Руководство по обслуживанию

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3. TECHNICAL BRIEF
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CONTROL REGISTER;ROM/SRAM
The Control register and ROM/SRAM are accessed from “Instantaneous write register”, “Delayed write
register”, and “Instantaneous read register”in the intermediate register.
In the control register, there is a register to control the following synthesizer mainly.
The voice parameter for FM(GM 128 DRUM 40 voices)and wave data for WT are stored in ROM.
SRAM is used at the download of arbitrary FM voice parameter and Wave data for WT.
moreover, it is used as storing buffer at the stream playback of PCM/ADPCM.
FIFO
This is an abbreviation of “First Input First Output” means the memory from which data is read in order of
data written.
There are 2 paths to write into FIFO in the Intermediate register.The “instantaneous write path” is for
accessing the control register and ROM/SRAM immediately,also “Delayed write path”is for accessing the
control register after managing time through the sequencer.FIFO size of Instantaneous path is 64 byte,
and its size of Delayed path is 512-byte.
SEQUENCER
This is for interpreting the contents of data which is written into the “Delayed write path” Generally,
“Music data” is written into the Delayed write path. It interprets the contents of music data and controls
the synthesizer after sequencer, and then plays the music.
Hybrid synthesizer
This device contains a built in polyphonic synthesizer that adopts a stereophonic hybrid system that
generate up to 64tones. FM synthesizer, WT synthesizer, stream playback, HV synthesizer, and AL
synthesizer are available.
DIGITAL AUDIO INPUT INTERFACE
This is a three wires type serial interface.The data length is 16bits.
DPLL SECTION/SAMPLING RATE CONVERTER SECTION
Sampling frequencies of signals from the digital audio interface section are changed into 48Khz.