3. TECHNICAL BRIEF
- 65 -
Write Operation
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deserted.
All device write operations are asynchronous, with CLK being ignored. During a write operation, address
and data are latched on the rising edge of WE # or CE#, whichever occurs first.
Output Disable
When OE# is deserted, device outputs D[15:0] are disabled and placed in a high-Impedance (High-Z)
state.
Standby Operation
When CE# is deserted the device is deselected and placed in standby, substantially Reducing power
consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#.
Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 µs after CE# is
deserted. During standby, average current is measured over the same time interval 5 µs after CE# is
deserted.
When the device is deselected (while CE# is deserted) during a program or erase operation, it continues
to consume active power until the program or erase operation is completed.
Reset Operation
As with any automated device, it is important to assert RST# when the system is reset. When the system
comes out of reset, the system processor attempts to read from the flash memory if it is the system boot
device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur
because the flash memory may be providing status information rather than array data.
Intel® flash memories allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register
is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z.
When RST# is asserted, the device shuts down the operation in progress, a process which takes a
minimum amount of time to complete.
When RST# has been deserted, the device is reset to asynchronous Read Array state.
Содержание KG920
Страница 3: ... 4 ...
Страница 48: ...3 TECHNICAL BRIEF 49 3 8 2 AFE Analog Front End Figure 3 22 ...
Страница 52: ...3 TECHNICAL BRIEF 53 3 8 5 MBGM01 5M CCD ISP Figure 3 25 ...
Страница 55: ...3 TECHNICAL BRIEF 56 3 8 6 MV8620 5M back end IC Multi Media Function Figure 3 26 ...
Страница 58: ...3 TECHNICAL BRIEF 59 3 9 MIDI IC YMU787 Figure 3 27 YMU787 BLOCKDIAGRAM ...
Страница 87: ...4 TROUBLE SHOOTING 88 Graph 4 8 BLUE RST Graph 4 9 DEBUG_TX RX Graph 4 10 PCM_SYNCS TX RX USC0 ...
Страница 96: ...4 TROUBLE SHOOTING 97 4 7 KEY backlight Trouble TEST POINT Q101 R122 Q101 LD101 LD119 Figure 4 38 Figure 4 39 ...
Страница 108: ...4 TROUBLE SHOOTING 109 CIRCUIT WAVEFORM Figure 4 59 Graph 4 11 Figure 4 60 Figure ...
Страница 109: ...4 TROUBLE SHOOTING 110 TEST POINT U602 FB602 U100 Q100 Q101 C113 C114 Figure 4 61 Figure 4 62 ...
Страница 111: ...Figure 4 65 Graph 4 12 4 TROUBLE SHOOTING 112 C102 C113 U101 Figure 4 66 C137 U103 TEST POINT WAVEFORM ...
Страница 112: ...4 TROUBLE SHOOTING 113 Figure 4 67 Figure 4 68 CIRCUIT ...
Страница 115: ...4 TROUBLE SHOOTING 116 WAVEFORM Graph 4 13 ...
Страница 139: ...6 BLOCK DIAGRAM 140 6 BLOCK DIAGRAM Figure 6 1 ...
Страница 148: ... 149 8 PCB LAYOUT ...
Страница 149: ... 150 8 PCB LAYOUT ...
Страница 150: ... 151 8 PCB LAYOUT ...
Страница 151: ... 152 8 PCB LAYOUT ...
Страница 152: ... 153 8 PCB LAYOUT ...
Страница 153: ... 154 8 PCB LAYOUT ...
Страница 154: ... 155 8 PCB LAYOUT ...
Страница 155: ... 156 8 PCB LAYOUT ...
Страница 163: ... 164 ...
Страница 194: ...Note ...
Страница 195: ...Note ...