3. TECHNICAL BRIEF
- 60 -
CPU INTERFACE
CPU interface is an 8-bit parallel.
4 control signal(/WR,/RD,/CS,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ),
totaling 13 pins are connected to the external CPU. This block controls the writing and
reading of data by the input polarity of control signal
INTERFACE REGISTER
These registers are able to access directly from the external CPU. There are 2 bytes spaces. The
Intermediate register can be accessed through the interface register.
INTERMEDIATE REGISTER
This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register. This
register is called “Intermediate register” since this exists in the middle of the interface register and the
Control register.
In the Intermediate register, there are some registers to control various functions.
(GPIO_12)
(GPIO_37)
(AUXCS1)
64POLY MIDI
68K
R201
R203
100K
C211
1000p
22n
C204
C202
0.1u
1000p
C224
27p
C206
C228
FB201
27p
0.1u
C203
1u
C225
0
R221
0.1u
C216
10u
C209
0
R220
120p
BGND
11
4
BYP
EN1
2
EN2
3
6
GND
5
NC1
NC2
7
8
NC3
1
VIN
10
VOUT1
VOUT2
9
C201
U201
MIC2211-GMYML
R204
30K
0.1u
C219
C222
1u
33K
R205
100K
R202
MIDI_CS
3.3K
2V8_MIDI
R208
R209
NA
C227
0.1u
NA
C212
2V8_MIDI
1u
C223
C226
MIDI_IRQ
1u
1u
C205
C220
0.1u
0.01u
E8
TXOUT
VREF
F7
_CS
H3
_IRQ
D4
H4
_RD
_RST
B4
_WR
J2
2V8_VEXT
C207
B2
MTR
NC1
A1
A8
NC2
J1
NC3
H5
PLLC
RXIN
C6
SDI
D1
B7
SPOUT1L
SPOUT1R
J8
B8
SPOUT2L
H8
SPOUT2R
SPVDDL
A6
J6
SPVDDR
A7
SPVSSL
SPVSSR1
H7
J7
SPVSSR2
B6
EXTIN
EXTOUT
D7
D6
GPIO0
C5
GPIO1
GPIO2
C1
GPIO3
C4
F6
HPC
C8
HPOUTL
C7
HPOUTR
HPVSS
D8
IOVDD1
H1
B3
IOVDD2
C2
LDE1_GPIO4
LED0
C3
LED2_GPIO5
B1
D3
LRCK
D5
F2
E3
D6
D7
E2
DVDD1
J4
DVDD2
A2
F1
DVDD3
J3
DVSS1
DVSS2
A3
DVSS3
E1
EQ1L
B5
J5
EQ1R
A4
EQ2L
EQ2R
G6
EQ3L
A5
H6
EQ3R
G7
EXC
YMU787
G4
A0
AVDD
G8
F8
AVSS
E6
BBL
BBR
E7
D2
BLCK
CLKI
G5
H2
D0
D1
G3
G2
D2
D3
F3
G1
D4
VBAT
U204
C217
0.1u
C221
1V8_MIDI
22u
1V8_MIDI
1u
C218
C208
1u
VBAT
47p
C214
C213
47p
M
SPK_P_SM
MIDI_SPK-
MIDI_HPLOUT
DATA08
WR_N
MIDI_RST
RD_N
MIDI_CS
ADD00
MIDI_IRQ
26MHZ
MIDI_HPROUT
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA09
Figure 3-28. YMU787 CIRCUIT DIAGRAM
Содержание KG920
Страница 3: ... 4 ...
Страница 48: ...3 TECHNICAL BRIEF 49 3 8 2 AFE Analog Front End Figure 3 22 ...
Страница 52: ...3 TECHNICAL BRIEF 53 3 8 5 MBGM01 5M CCD ISP Figure 3 25 ...
Страница 55: ...3 TECHNICAL BRIEF 56 3 8 6 MV8620 5M back end IC Multi Media Function Figure 3 26 ...
Страница 58: ...3 TECHNICAL BRIEF 59 3 9 MIDI IC YMU787 Figure 3 27 YMU787 BLOCKDIAGRAM ...
Страница 87: ...4 TROUBLE SHOOTING 88 Graph 4 8 BLUE RST Graph 4 9 DEBUG_TX RX Graph 4 10 PCM_SYNCS TX RX USC0 ...
Страница 96: ...4 TROUBLE SHOOTING 97 4 7 KEY backlight Trouble TEST POINT Q101 R122 Q101 LD101 LD119 Figure 4 38 Figure 4 39 ...
Страница 108: ...4 TROUBLE SHOOTING 109 CIRCUIT WAVEFORM Figure 4 59 Graph 4 11 Figure 4 60 Figure ...
Страница 109: ...4 TROUBLE SHOOTING 110 TEST POINT U602 FB602 U100 Q100 Q101 C113 C114 Figure 4 61 Figure 4 62 ...
Страница 111: ...Figure 4 65 Graph 4 12 4 TROUBLE SHOOTING 112 C102 C113 U101 Figure 4 66 C137 U103 TEST POINT WAVEFORM ...
Страница 112: ...4 TROUBLE SHOOTING 113 Figure 4 67 Figure 4 68 CIRCUIT ...
Страница 115: ...4 TROUBLE SHOOTING 116 WAVEFORM Graph 4 13 ...
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