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Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
The DBB External Bus Interface provides a memory-mapped interface to external devices such as NOR Flash
, NAND Flash, SRAM, SDRAM, PSRAM, and other custom devices.
The External Memory Interface contains three distinct memory controllers: a NAND Flash Controller (NFC),
an SDRAM Controller (SDC), and the External Bus Controller (EBC).
These three controllers share the external pins. They also share an arbiter through which the DMA controlle
rs (via DDBUS, ADBUS, and DMABUS) and the processor cores (via DSPBUS and MCUEBUS) access external
devices. The following figure shows the external memory interface block diagram.
The following table shows the pin list for the external memory interface which supported by Main Base
Band chipset(AD6725).
Figure 3-6-2 DBB EBU SUBSYSTEM BLOCK DIAGRAM