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IC601 (M12L16161A) : SDRAM
38
V
1
50
2
49
V
DQ0
DQ15
3
48
DQ1
DQ14
5
46
DQ2
DQ13
6
45
DQ3
DQ12
4
47
V
DD
SSQ
V
SSQ
7
44
V
DDQ
V
DDQ
8
43
DQ4
DQ11
9
10
11
12
42
DQ5
DQ10
41
V
SSQ
V
SSQ
40
DQ6
DQ9
13
14
38
V
DDQ
V
DD
V
SS
V
DDQ
37
LDQM
N.C/RFU
15
36
WE
UDQM
16
35
CAS
CLK
17
34
RAS
CKE
18
33
CS
N.C
19
32
BA
A9
20
31
A10/AP
A8
21
30
A0
A7
22
29
A1
A6
23
28
A2
A5
24
27
A3
A4
25
26
39
DQ7
DQ8
SS
Overview
The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2x 524,288
words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle
control with the use of system clock I/O transactions are possible on every clock cycle. Range for operating
frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
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PIN CONFIGURATION (TOP VIEW)
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH