30
•
Pin Functions
256 241
Pin
name
System controller
external connection
I/O
Destination
Description
1 1 T2
NOE
NRD(I)
O
Flash
Read signal output to flash
2 2 U3
NCE
NCS(I)
O
Flash Chip
select
signal
output
to
flash
3 3 T1
FADR0
CPUADR0(I)
O
Flash Address
output
to
flash
4 4 R2
FADR1
CPUADR1(I)
O
Flash Address
output
to
flash
5 5 T4
FADR2
CPUADR2(I)
O
Flash Address
output
to
flash
6 6 R1
FADR3
CPUADR3(I)
O
Flash Address
output
to
flash
7 7 P5
FADR4
CPUADR4(I)
O
Flash Address
output
to
flash
8 8 - V
DD3
Power
supply
-
V
DD
(3.3 V)
9 9 - V
DD15
Power
supply
-
V
DD
(1.5 V)
10 10 - V
SS
GND
-
V
SS
11 11 M4 FADR5
CPUADR5(I)
O
Flash Address
output
to
flash
12 12 P1 FADR6
CPUADR6(I)
O
Flash Address
output
to
flash
13 13 T3 FADR7
CPUADR7(I)
Flash Address
output
to
flash
14 14 N2 FADR8
CPUADR8(I)
O
Flash Address
output
to
flash
15 15 P4 P7/FADR17 NINT0(O)
I/O Flash
Address output to general-purpose port/flash
16 16 N1 P8/FADR18 CPUADR17(I)
I/O Flash
Address output to general-purpose port/flash
17 17 N4 P17/FADR19
I/O Flash
Address output to general-purpose port/flash
18 18 P3 NWE
NWR(I)
O
Flash
Write signal output to flash
19 19 K5 FADR9
CPUADR9(I)
O
Flash Address
output
to
flash
20 20 M2 FADR10
CPUADR10(I)
O
Flash Address
output
to
flash
21 NC NC _V
DD3
Power
supply
-
V
DD
(3.3V)
22 21 - V
SS
GND
-
V
SS
23 22 L4 FADR11
CPUADR11(I)
O
Flash Address
output
to
flash
24 23 M3 FADR12
CPUADR12(I)
O
Flash Address
output
to
flash
25 24 M1 FADR13
CPUADR13(I)
O
Flash Address
output
to
flash
26 25 K4 FADR14
CPUADR14(I)
O
Flash Address
output
to
flash
27 26 L3 MMOD
I
-
Test mode selection signal
28 27 K3 FADR15
CPUADR15(I)
O
Flash Address
output
to
flash
29 28 L1 DRAMV
DD15
Power
supply
-
DRAM power supply (1.5 V)
30 29 L2 VOUT
Regulator output (1.5 V)
31 30 K1 DRAMV
DD33
Power
supply
-
DRAM Power supply(3.3V)
32 31 J1 DRAMV
SS
GND
-
V
SS
for DRAM use
33 NC NC _V
SS
GND
-
V
SS
34 32 J4
TxD/EXTRG0/M
DATA
I/O Debug
Trigger pin for serial transmission/Dwire use