Lattice CrossLink-NX PCIe, Руководство пользователя

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CrossLink-NX PCIe Bridge Board Basic Demo
User Guide
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5.4. Running PCIe Memory Access Demo
The Memory tab provides several elements to control the read-write process. Table 5.4 provides descriptions of
Memory tab.
When this tab is clicked the whole contents of the EBR memory is displayed in Memory Contents table, based on the
radio button selected. Data access can be specified as 8 bit, 16 bit, or 32 bit operations by selecting Data Size. Access is
to the selected Base Address Register (BAR).
Data can be written to the registers by using Write button. Specify the BAR offset to start writing at and the hex data in
the Data field. Data size should match the data width selected at the top to the page.
Figure 5.5. PCIe Test Application Memory Tab
Table 5.4. Memory Tab
Feature Description
Memory Space Indicates the base address register (BAR) memory space to access.
8-bit, 16-bit,
32-bit
These radio buttons control the size of data that is being written or read.
Memory Tests
In Memory Test mode, sequential data is written and read back to check that all locations of EBR properly
accessed.
Test mode
combo box
There are two test modes, single and continuous. In single mode, the write read operation is done only once for
all memory locations, while in continuous mode, the write read operation is done in a loop until you choose to
stop.
Run Runs the selected test in background thread.
Status Shows the result of running test.
Memory
Contents
Displays memory contents.