CrossLink-NX PCIe Bridge Board Basic Demo
User Guide
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FPGA-UG-02145-1.0
4.2.1.
PCIe Hard IP
The PCIe hard IP has three layers: physical layer, data link layer & transaction layer. On power up, the physical layer is
responsible for doing link training. Once the training is completed a pl_link_up signal is asserted, indicating that the
physical layer is up. The Physical layer is also responsible for the rate negotiation, 8b/10b encoding/decoding (gen1 and
gen2), byte striping, scrambling/descrambling, and packet serialization/deserialization.
The Data link layer is responsible for the creation and transmission of DLLPs (data link layer packet) and decoding these
received packets. This layer is also responsible for error detection and retransmission (Ack/Nak protocol).
The Transaction layer is responsible for transmitting and receiving TLPs (transaction layer packet). These packets can be
Memory read/write, I/O read/write, messages and others
The PCIe hard IP is hardened into the FPGA itself, and does not consume fabric resources when used.
The PCIe hard IP has three signals u_pl_link_up, u_dl_link_up, u_tl_link_up that indicate the link-up status of the three
previously mentioned layers.
4.2.2.
BAR RAM
A 4 KB BAR memory is implemented on the application side to store the data. Through software, you can read or write
data from/to this RAM.
4.2.3.
Display Controller
The BAR offset address 0x0 is mapped to the three 7-segment displays on the CL_NX PCIe bridge board.
