CrossLink-NX PCIe Bridge Board Basic Demo
User Guide
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FPGA-UG-02145-1.0
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4.2.
FPGA Design
A user interface application is provided for demonstrating the PCIe Basic demo. Application software is developed using
a layered architecture consisting of the following layers:
User interface application
Protocol library
Driver
PCIe Driver for BAR memory read write
PCIe Bus driver for Lattice Endpoint
User Interface Application
Protocol Library
BAR Memory Driver
PCIe Bus Driver
Figure 4.2. PCIe Basic Demo SW Design
PCIe hard IP is used on the FPGA side to implement the PCIe endpoint. At the transaction layer, logic implemented in
the pcie_tx_engine and pcie_rx_engine modules are used to handle communication to/from the PCIe hard IP
transaction layer, which consists primarily of encoding TLPs for transmission, and decoding received TLPs and storing
this data in local memory. An application, 4KB of Bar memory and 3x7 Segment displays are used with single PCIe
Function. Apart from that, the LMMI interface is used for initial re-configuration of the PCIe IP.
PCIe_app_wrapper
FPGA_TOP
PCIe_ep_mem_top
RAM
7 Segment
PCIe_rx_engine
PCIe_rx_engine
7 Segment
VC_rx
VC_tx
PCIe IP
PCIe X1 Lane
Figure 4.3. PCIe Basic Demo FPGA Design
