USB3-GbE VIP I/O Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
FPGA-EB-02016-1.0
2.
Functional Description
The USB3-GbE VIP IO Board provides USB3 and Gigabit Ethernet connectivity for the ECP5 VIP Processor Board. The
Gigabit Ethernet Phy and the USB3 controller work independently.
TI GigE Phy
DP 83867R
RJ45
MDIO
RGMII
SYS Reset
Data
USB3 FX3 Controller
CYUSB3014
Two
60-Pin
Connector
J1/J2
Micro
USB
Control
Clock
USB
Parallel Data
Figure 2.1. Functional Block Diagram
2.1.
Switches and Buttons
The push button switch, SW1, is connected to the CTL10_GPIO signal of the FX3 USB Controller. The push button
switch, SW2, is connected to the System Reset of the board. Pressing SW2 provides logic 0 to the TI DP83687 and
CYUSB3014 Reset pin. The RESET signal is also connected to GSRN on connecter J1, allowing SW2 to control the reset
signal for other connected boards.
2.2.
Gigabit Ethernet Interface
The RJ45 connector, J3, provides Gigabit Ethernet connectivity via a standard Cat6 Ethernet cable.
2.3.
USB3 Interface
The USB 3.0 Micro-B connector, J4, provides USB connectivity via a Micro USB 3.0 cable.
