USB3-GbE VIP I/O Board
Evaluation Board User Guide
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10
FPGA-EB-02016-1.0
5.
User LEDs and Headers
Eight discrete LEDs (light-emitting diodes) are available to the user.
Table 5.1. User LEDs
Signal
LED #
Source
Color
LED1
D1
1.2 V LDO
Green
LED2
D2
12 V
Green
LED3
D3
5.0 V
Green
LED4
D4
Activity
Yellow
LED5
D5
Speed 1000
Green
LED6
D6
Link up
Blue
LED7
D7
1.1 V LDO
Green
LED8
D8
FX3 user LED
Blue
The USB3-GbE VIP IO Board has four 3-pin configuration headers. Header J2 allows to configure the applied voltage to
the board. The user can select either 3.3 V or 2.5 V. Header J3, J4, and J5 provide the bootstrapping options for the
Boot selection of the FX3 USB controller.
Table 5.2. Header J2
Description
Header J2 Pin 1
Header J2 Pin2
Header J2 Pin 3
VCCIO
V2R5
VIO
V3R3
Table 5.3. Header J3
Description
Header J3 Pin 1
Header J3 Pin2
Header J3 Pin 3
FX3 Boot Selection
VIO
PMODE0
GND
Table 5.4. Header J4
Description
Header J4 Pin 1
Header J4 Pin2
Header J4 Pin 3
FX3 Boot Selection
VIO
PMODE1
GND
Table 5.5. Header J5
Description
Header J5 Pin 1
Header J5 Pin2
Header J5 Pin 3
FX3 Boot Selection
VIO
PMODE2
GND
