USB3-GbE VIP I/O Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02016-1.0
5
Upstream
Connector (J1)
Upstream
Connector (J2)
TI GigE Phy
JTAG Debugger of FX3
FX3 USB3 Controler
Figure 1.2. Bottom View of USB3-GbE VIP IO Board
1.1.
Further Information
The following references provide detailed information on the USB3-GbE VIP IO Board:
Appendix A. USB3-GbE VIP IO Board Schematics
Appendix B. USB3-GbE VIP IO Board Bill of Materials
For more information on boards and kits available for the VIP (Video Interface Platform) system visit
www.latticesemi.com/vip.
For details on the Texas Instruments DP83867IR Gigabit Ethernet PHY, visit the Texas Instruments website at
www.ti.com.
For details on the Cypress FX3 USB3.1 controller, visit the Cypress website at
www.cypress.com
.
