MachXO 2280 Breakout Board Evaluation Kit
Evaluation Board User Guide
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FPGA-EB-02038-1.2
Table 7.1. Breakout Board Components and Interfaces
Component/Interface
Type
Schematic Reference
Description
Circuits
USB Controller
Circuit
U2: FT2232H
USB-to-JTAG interface and dual USB UART/FIFO
IC
USB Mini-B Socket
I/O
J1:USB_MINI_B
Programming and debug interface
Components
LCMXO2280C
PLD
U4: LCMXO2280C-3FTN256C
2280-LUT device packaged in a 17 x 17mm,
256-ball ftBGA.
Interfaces
LED Array
Output
D8-D1
Red LEDs
Eight 2x20 Header
Landings
I/O
J3: header_2x20
J4: header_2x20
J5: header_2x20
J6: header_2x20
J7: header_2x20
J8: header_2x20
J9: header_2x20
J10: header_2x20
User-definable I/O
1x8 Header Landing
I/O
J1: header_1x8
Optional JTAG interface
4-Hole Prototype Area
—
—
Prototype area 100mil centered holes.
7.2.
Subsystems
This section describes the principle sub systems for the Breakout Board in alphabetical order.
7.2.1.
Clock Sources
All clocks for the counter demonstration designs originate from the MachXO 2280 PLD on-chip oscillator. You may use
an expansion header landing to drive a PLD input with an external clock source.
7.2.2.
Expansion Header Landings
The expansion header landings provide access to user GPIO, primary inputs, clocks, and VCCO pins of the MachXO
2280. The remaining pins serve as power supplies for external connections. Each landing is configured as one 2 × 20
100 mil.
Table 7.2. Expansion Connector Reference
Item
Description
Reference Designators
J3, J4, J5, J6, J7, J8, J9, J10
Part Number
header_2x20