26
ispClock5400D Evaluation Board
Lattice Semiconductor
User’s Guide
Figure 27. Bank 0 MLVDS with On-Board Termination
ispClock5406D Standard Evaluation Board
R16
R17
0
0
R23
33
R24
33
R25
22
R26
22
R28
0.1uF
R29
0.1uF
R30
34
R31
34
BANK_0P
J3
J4
BANK_0N
50
5pF
50
5pF
50 ohms / 64.3 mm
m
c
1
9
/
s
m
h
o
0
5
m
m
3
.
4
6
/
s
m
h
o
0
5
SMA to BNC Cable
SMA to BNC Cable
On Board T-Line
On Board T-Line
MLVDS
Buffers
50 ohms / 91 cm
R18
100
ispClock
Scope
LVPECL
LVPECL drivers require a DC bias at the driven end of the T-Line and 100 ohms differential termination at the
receiving end of the T-Line. The DC bias is usually provided by 50 ohms impedance to VCCO-2V. This will both
bias the output buffers and terminate one end of the T-Line to minimize reflections. In Figure 28, R19 with R21 and
R20 with R22 function as voltage dividers to provide the required bias and termination. With a 3.3V VCCO supply
the divided voltage is 1.3V and the Thevenin-equivalent impedance seen by the T-Line is 50 ohms (82 || 124 = 50).
At the receiving end of the on-board T-Line, the termination and scope sense circuit is identical to that of LVDS cir-
cuit discussed above.
Figure 28. Bank 0 LVPECL with On-Board Termination
ispClock5406D Standard Evaluation Board
R16
R17
0
0
R23
33
R24
33
R25
22
R26
22
R28
0.1uF
R29
0.1uF
R30
34
R31
34
BANK_0P
J3
J4
BANK_0N
50
5pF
50
5pF
50 ohms / 64.3 mm
m
c
1
9
/
s
m
h
o
0
5
m
m
3
.
4
6
/
s
m
h
o
0
5
SMA to BNC Cable
SMA to BNC Cable
On Board T-Line
On Board T-Line
LVPECL
Buffers
50 ohms / 91 cm
R21
124
R19
82
R22
124
R20
82
VCCO
VCCO
ispClock
Scope
SSTL15/SSTL18
SSTL15 and SSTL18 both utilize the same termination network, which is 50 ohms at the receiving end of the T-Line
to VCCO divided by 2. Figure 29 shows that for the ispClock5406 a source termination of 20 ohms is also recom-
mended and provided by R16 and R17. At the load end of the non-inverting T-Line the output supply VCCO is
divided in half using the network of R33 on the top side and R23, R25, R28, and the scope input impedance on the
bottom side. The lower half of this divider is a 5:1 sub-divider for viewing the waveform at the scope. The inverting
output has a similar circuit to provide a balanced load at the end of the T-Line and to support viewing both sides of
the differential signal.
