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ispClock5400D Evaluation Board

Lattice Semiconductor

User’s Guide

Specify REF Frequency:

100

then click the

Internal Feedback, Modify...

button.



The External Feedback Setting dialog appears.

Select

Internal Feedback

, select

Feedback taken from V-Divider 8

, and click

From the PLL Core Settings dialog, click

From the Edit Symbol dialog, select

USER PINS

and click the

Edit...

button.



The USER Pin Function Allocation dialog appears.

Select

PLL_BYPASS = PLL

then click the

button.



The USER Pin Summary dialog appears. Click the

button.

10. From the Edit Symbol dialog select

Output BANK_0

then click the

Edit...

button.



The Output Settings for BANK_0 & Bank_1 dialog appears.

11. Click the

Source, Modify...

button.



The Output Pair Source Setting dialog box appears.

12. For BANK_0, choose

V-Divider-8

, choose,

From V-Divider

, and click the

button.

From the Output Settings for BANK_0 & BANK_1 dialog, select the following options for BANK_0:

Output Type:

LVPECL

Output Enable:

Always Enabled

Select the following option for BANK_1:

Output Enable:

Always Disabled

Click the

button.

13. From the Edit Symbol dialog select

Output BANK_2

then click the

Edit...

button.



The Output Settings for BANK_2 & Bank_3 dialog appears.

14. From the Output Settings for BANK_2 & BANK_3 dialog, select the following options for BANK_2:

Output Enable:

Always Disabled

Select the following option for BANK_3:

Output Enable:

Always Disabled

Click the

button.

15. From the Edit Symbol dialog select

Output BANK_4

then click the

Edit...

button.



The Output Settings for BANK_4 & Bank_5 dialog appears.

16. From the Output Settings for BANK_4 & BANK_5 dialog, select the following options for BANK_4:

Output Enable:

Always Disabled

Select the following option for BANK_5:

Output Enable:

Always Disabled

Click the

button.

17. From the Edit Symbol dialog, click

Close

18. Click the

Download

icon on the top toolbar.



The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.

19. Click



PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.

Содержание ispClock5400D

Страница 1: ...July 2010 Revision EB50_01 2 ispClock5400D Evaluation Board User s Guide ...

Страница 2: ...extremely low propagation delay zero delay from input to output using the on chip low jitter high performance phase locked loop PLL A set of four fixed dividers can be used to generate four frequencies derived from the PLL clock These dividers are designed in powers of 2 only 2 4 8 and 16 The clock output from any of the V dividers can then be routed to any clock output pair through the output rou...

Страница 3: ...atics of the board For a complete list of the various connections and interfaces used on the ispClock5400D Evaluation Board please refer to the schematics in Appendix A The ispClock5400D Evaluation Board is 100 lead free and RoHS compliant as Lattice Semiconductor Corpora tion is sensitive to environmental issues Additional resources relating to the ispClock5400D Evaluation Board are available on ...

Страница 4: ...sure ispClock5400D period jitter per formance with a signal integrity analyzer SERDES Reference Clock A co demonstration with the LatticeECP3 Serial Protocol or I O Protocol boards Video Reference Clock A co demonstration with the LatticeECP3 Video Protocol board Note It is possible that you will obtain your evaluation board after it has been reprogrammed To restore the factory default demo and pr...

Страница 5: ...pears 5 Browse the Base_Demo_CLK5406D PAC project and choose Open The ispPAC CLK5406D schematic view appears Figure 2 ispClock5406D Schematic View 6 Choose File Save As The Save As dialog appears 7 Specify File name Base_Demo_CLK5406D_rev PAC and click Save PAC Designer creates a new revision of the project 8 Choose View ispCLK Output Summary The Output Summary Sheet appears The default demo will ...

Страница 6: ...s to 50 Ohm termination For this mode we use LVDS and the 50 Ohm termination on each scope channel The waveforms shown are using 3 long RG 316 cables with the SMA connectors If the equipment has high impedance probes or a differential probe make sure that the LVDS BANK outputs have 100 Ohm termination from BANK_P to BANK_N When operating properly you should see four waveforms on the scope as shown...

Страница 7: ...t The demo uses the default factory board assembly with zero Ohm resistors connecting the SMA terminals directly to the output banks This approach is for the demo only Some of the waveforms displayed will only show the positive side of each BANK output on the scope for simplicity and timing measurements Modify Clock Time Skew This section describes the procedure to modify the time skew of the ispC...

Страница 8: ...5406D Skew Editor The Skew Editor allows you to graphically configure the ispClock5406D output skew Waveforms are color coded All disabled outputs are indicated in gray while active outputs are indicated in green or white Skew is adjusted by dragging the waveform edges with the mouse Dragging the waveform specified as feedback high lighted in green will move every other waveform in the opposite di...

Страница 9: ...K PAC Designer reprograms the evaluation board with the updated JEDEC programming file 9 Note the updated scope display This waveform shows the de skewed outputs Figure 9 Scope Plot De skewed Outputs The programmable ispClock5406D Time Skew feature allows the device to account for very small incremental delays and correct for system board trace level effects The function is used to correct timing ...

Страница 10: ...ut Block The Output Settings for BANK_2 BANK_3 dialog box appears Figure 10 Output Settings for BANK_2 BANK_3 2 Choose Inverted Yes from the BANK_2 section of the dialog and click OK PAC Designer updates the output setting of the project 3 Click the Download icon on the top toolbar The Frequency Summary dialog appears and reports the Reference and VCO frequency settings 4 Click OK PAC Designer rep...

Страница 11: ... phase skew will be advanced four PUD units or 1 24 ns To modify clock phase skew 1 From PAC Designer choose Edit Symbol The Edit Symbol dialog appears 2 Choose Skew Manager and click the Edit button Phase Skew Manager appears 3 Choose the following options Skew Step Fine BANK_2 Phase Skew 4PUD Click OK PAC Designer updates the phase skew for the project 4 Click the Download icon on the top toolba...

Страница 12: ...s to adjust the on chip REFSEL signal In this case the user signal input USER3 acts as a mux control over REFA and REFB input reference clocks To modify the reference clock source input 1 From PAC Designer double click the USER Signal Routing Block The USER Pin Function Allocation dialog appears 2 Note the REFSEL function input is set to the USER3 pin input This allows an external control over the...

Страница 13: ...ocks on every bank output pair Upon device reset the device returns to the configuration stored in E2 CMOS The PAC Designer I2 C Design Utility for the ispClock5406D provides a software interface to the ispClock5406D I2 C registers such as output group and PLL controls The demo will apply all the changes you performed by reprogramming the device in the earlier procedures of the user s guide To set...

Страница 14: ...or User sGuide Figure 14 Design Utilities Dialog Box 6 Select ispClock_5406_I2C_Utility exe and click OK The ispClock5406D I2 C Utility appears Figure 15 ispClock5406D I2 C Utility 7 Choose Options I2C Interface The Cable and I O Port Setup Dialog appears ...

Страница 15: ...igure 16 ispClock5406D I2 C Address Dialog Box 14 Select 7Fh from the I2 C Address list and click OK The I2 C Utility sets the I2 C address for the ispClock5406D The 5406D I2 C device address must match what is stored in E2 CMOS when the device program was down loaded with the JTAG pattern Once the address is set full communication can be established with the device using the I2 C interface Note M...

Страница 16: ... delay in cables is about 50 80ps 3 From the ispClock5406D I2 C Utility click the Output Group 1 button The ispClock5406D Output Group 1 Control dialog appears Figure 18 ispClock5406D Output Group 1 Control The I2 C utility output group control supports in system changes to V Dividers settings routing for each bank Phase Skew enable Output Bank enable OE control ...

Страница 17: ...the register and active at this point unless an I2 C soft or full reset or hardware power on reset occurs For more information on I2 C control registers see the ispClock5400D Family Data Sheet 8 From the ispClock5406D Output Group 1 Control dialog click the OK button You may wish to experiment with the I2 C utility interface to apply the same clock inversion and phase skew changes as documented in...

Страница 18: ...rom a full reset the device reverts back to the configuration state that is defined and stored in E2 CMOS 8 Click OK Note the scope display changes to reflect the original waveform pattern produced by the initial ispClock5406D device programming You have completed the ispClock5406D Base Demo You can try other in system device configurations using the I2 C utility or modify the PAC Designer project...

Страница 19: ... for BANK_0 Output Type LVPECL Output Enable Always Enabled Select the following option for BANK_1 Output Enable Always Disabled Click the OK button 13 From the Edit Symbol dialog select Output BANK_2 then click the Edit button The Output Settings for BANK_2 Bank_3 dialog appears 14 From the Output Settings for BANK_2 BANK_3 dialog select the following options for BANK_2 Output Enable Always Disab...

Страница 20: ... describes the low jitter perfor mance characteristics of the ispClock5406D clock output in the context of a 270 MHz SDI video application This demonstration requires Lattice Intellectual Property for the LatticeECP3 FPGA Please contact Lattice for more information on how to obtain the project source Download Demo Designs The ispClock5406D base demo is preprogrammed into the evaluation board howev...

Страница 21: ... to export a JEDEC le which can be used with ispVM to program the evaluation board The board must be un powered when connecting disconnecting or reconnecting the ispDOWNLOAD Cable Always connect the ispDOWNLOAD Cable s GND pin black wire before connecting any other JTAG pins Failure to follow these procedures can in result in damage to the ispClock5406D device and render the board inoperable Conne...

Страница 22: ...Figure 21 Change Programming Cable Interface Dialog Box 4 From the Programming Cable Interface list select Uses PC USB and click OK The Cable and I O Port Setup dialog appears Figure 22 Cable and I O Port Setup Dialog Box 5 Click Settings The USB Setting dialog appears ...

Страница 23: ...ialog boxes PAC Designer must be restarted to load the port drivers for the system Figure 24 PAC Designer JTAG Prompt 7 Click OK to dismiss the message 8 Close PAC Designer Programming the Evaluation Board To repgrogram the ispClock5400D Evaluation Board 1 Run PAC Designer 2 Open the demo pac project file 3 Choose Tools Download The Frequency Summary dialog appears and reports the Reference and VC...

Страница 24: ...as the clock reference and allows the PLL to lock to that frequency Table 1 To the Left SW1 Section To the Right 0 1 1 REFA_EN 0 2 1 REFB_EN 0 3 1 REF SEL LOCK LED 4 N C USER0 Unused 5 Unused 2 5V 6 3 3V 1 8V 7 3 3V 1 5V 8 3 3V DIP Switch Functions Input Output Connections The evaluation board incorporates tapered transitions from the SMA connectors to the matched 50 ohm microstrip transmission li...

Страница 25: ...s are populated with resistors but in other cases DC blocking capacitors The on board T Line and termination networks support differential viewing of the signal at the end of the T Line In cases where only one output of the signal is to be viewed connected to a scope the other output should be terminated with a similar length of cable and a 50 ohm terminator LVDS Low Voltage Differential Signal LV...

Страница 26: ... on board T Line the termination and scope sense circuit is identical to that of LVDS cir cuit discussed above Figure 28 Bank 0 LVPECL with On Board Termination ispClock5406D Standard Evaluation Board R16 R17 0 0 R23 33 R24 33 R25 22 R26 22 R28 0 1uF R29 0 1uF R30 34 R31 34 BANK_0P J3 J4 BANK_0N 50 5pF 50 5pF 50 ohms 64 3 mm m c 1 9 s m h o 0 5 m m 3 4 6 s m h o 0 5 SMA to BNC Cable SMA to BNC Cab...

Страница 27: ...on ispClock R16 R17 25 25 R23 71 5 R24 71 5 R25 45 3 R26 45 3 R28 R29 R30 0 R31 0 BANK_0P J3 J4 BANK_0N Scope 50 5pF 50 5pF 50 ohms 64 3 mm 50 ohms 64 3 mm 50 ohms 91 cm SMA to BNC Cable SMA to BNC Cable On Board T Line On Board T Line ispClock5406D Standard Evaluation Board SSTL Buffers 50 ohms 91 cm R27 0 18 7 18 7 VCCO VCCO R33 100 R32 100 eHSTL HSTL For eHSTL and HSTL the source termination re...

Страница 28: ... 5V power supply capable of providing one ampere or more The board can be powered either by a wall adapter with a 2 5mm coaxial power plug at J13 or from a bench supply with banana plugs at J11 and J12 Once onboard the supply is regulated U2 to provide the 3 3V supply needed for VCCD VCCA and VCCJ A second adjustable regulator U3 provides the VCCO for banks 3 and 5 and it is programmable using the...

Страница 29: ...he ispClock5406D device and board connections Table 2 Pin Information and Bank Summary Pin Pin Function Bank Board Connection 1 GNDO_5 5 GND 2 BANK_5P 5 BANK_5P 3 BANK_5N 5 BANK_5N 4 VCCO_5 5 VCCO_5 5 VCCO_4 4 VCCO_4 6 BANK_4P 4 BANK_4P 7 BANK_4N 4 BANK_4N 8 GNDO_4 4 GND 9 GNDO_3 3 GND 10 BANK_3P 3 BANK_3P 11 BANK_3N 3 BANK_3N 12 VCCO_3 3 VCCO_3 13 GNDA GND 14 REFAVTT GND 15 REFAN REFA_N 16 REFAP ...

Страница 30: ...k5400D Differential Clock Buffer EB44 LatticeECP3 Serial Protocol Board User s Guide EB39 LatticeECP3 Video Protocol Board User s Guide Ordering Information Description Ordering Part Number China RoHS Environment Friendly Use Period EFUP ispClock5400D Evaluation Board PACCLK5406D S EVN 34 BANK_0N 0 BANK_0N 35 BANK_0P 0 BANK_0P 36 GNDO_0 0 GND 37 VCCJ VCC 38 TDO TDO 39 TMS TMS 40 TCK TCK 41 TDI TDI...

Страница 31: ...ber 2009 01 1 Added Troubleshooting section July 2010 01 2 Updated part numbers for the LatticeECP3 Serial Protocol Board and LatticeECP3 Video Protocol Board in the Hardware Requirements sec tion 2010 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or register...

Страница 32: ...Evaluation Board B Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project Thursday February 19 2009 A B 9 1 ispCLOCK5406D ispClock5406D Lab Evaluation Board B Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 9 Sheet 9 Sheet 2 Sheet 3 Sheet 2 Connect DIEPAD to ground plane with 5 or more vias R34 470 R34 4...

Страница 33: ...lator A ispClock5406D Lab Evaluation Board B Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project Thursday February 19 2009 A B 9 2 ispClock5406D Reference Oscillator A ispClock5406D Lab Evaluation Board B LVCMOS 220 X 220 X LVDS X X X X LVPECL 124 82 124 82 X Do Not Install Xtal Output R1 R2...

Страница 34: ...c Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project Thursday February 19 2009 A B 9 3 ispClock5406D Reference Oscillator B ispClock5406D Lab Evaluation Board B Xtal Output R5 R6 R7 R8 LVCMOS 220 X 220 X LVDS X X X X LVPECL 124 124 82 82 X Do Not Install REFB Source R9 R10 R11 R12 R13 R14 5x7 X2 0 0 X X X X Ca...

Страница 35: ...k 0 Termination and Connectors ispClock5406D Lab Evaluation Board B Bank Output R16 R17 R18 R19 X X 0 0 S D V L SSTL15 18 20 20 X X HCSL 33 33 X 50 X Do Not Install R20 R21 R22 R23 Loading On Board On Board On Board R24 R25 R26 R27 X X X 33 X X X 71 5 50 X X 0 33 22 22 X 71 5 45 3 45 3 0 0 X X X R28 R29 R30 R31 0 1u 0 1u 34 34 18 7 18 7 0 0 950 950 0 0 64 3mm X 0 0 1 0 0 S D V L M 4 3 4 3 u 1 0 u ...

Страница 36: ...k 2 Termination and Connectors ispClock5406D Lab Evaluation Board B X x 0 0 S D V L M X X X 0 0 X X X d r a o B f f O 0 0 0 0 X X Bank Output R36 R37 R38 R39 X X 0 0 S D V L SSTL15 18 20 20 X X HCSL 33 33 X 50 R40 R41 R42 R43 Loading On Board On Board On Board R44 R45 R46 R47 X X X 33 X X X 71 5 50 X X 0 33 22 22 X 71 5 45 3 45 3 0 0 X X X R48 R49 R50 R51 0 1u 0 1u 34 34 18 7 18 7 0 0 950 950 0 0 ...

Страница 37: ...k 3 Termination and Connectors ispClock5406D Lab Evaluation Board B X x 0 0 S D V L M X X X 0 0 X X X d r a o B f f O 0 0 0 0 X X Bank Output R56 R57 R58 R59 X X 0 0 S D V L SSTL15 18 20 20 X X HCSL 33 33 X 50 R60 R61 R62 R63 Loading On Board On Board On Board R64 R65 R66 R67 X X X 33 X X X 71 5 50 X X 0 33 22 22 X 71 5 45 3 45 3 0 0 X X X R68 R69 R70 R71 0 1u 0 1u 34 34 18 7 18 7 0 0 950 950 0 0 ...

Страница 38: ... 5 Termination and Connectors ispClock5406D Lab Evaluation Board B X x 0 0 S D V L M X X X 0 0 X X X d r a o B f f O 0 0 0 0 X X Bank Output R76 R77 R78 R79 X X 0 0 S D V L SSTL15 18 20 20 X X HCSL 33 33 X 50 R80 R81 R82 R83 Loading On Board On Board On Board R84 R85 R86 R87 X X X 33 X X X 71 5 50 X X 0 33 22 22 X 71 5 45 3 45 3 0 0 X X X R88 R89 R90 R91 0 1u 0 1u 34 34 18 7 18 7 0 0 950 950 0 0 6...

Страница 39: ...oard Rev Project Thursday February 19 2009 A B 9 8 12V to 5V Input 3 3V VCC Output and VCCO Adjustable ispClock5406D Lab Evaluation Board B 1 5 Square Inch PCB Heat Sink 0 5 Square Inch PCB Heat Sink Switch VCCO NONE 1F 1G 1H 3 30V 2 50V 1 80V 1 50V Mounting Holes R55 73 2K R55 73 2K C29 100nF C29 100nF Q14 PZT4401 SOT 223 Q14 PZT4401 SOT 223 R54 301K R54 301K U3 TPS77701 U3 TPS77701 IN 3 IN 4 GND...

Страница 40: ... B 9 9 Test JTAG and I2C Interface and Connectors ispClock5406D Lab Evaluation Board B Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project Thursday February 19 2009 A B 9 9 Test JTAG and I2C Interface and Connectors ispClock5406D Lab Evaluation Board B R98 4k7 R98 4k7 R99 4k7 R99 4k7 R102 4 ...

Страница 41: ... pin header 22 28 4104 18 8 J1 6 J17 J18 SMA Connector PCB End Launch 142 0701 801 19 8 L1 8 300 ohm Signal Ferrite SMD 0805 LI0805G301R 10 20 2 L9 L10 60 ohm Ferrite Bead SMD 0603 HI0603P600R 10 21 1 X1 100 MHz Clock Source ECS 3953M 1000BN 22 1 X2 156 25 MHz Clock Source CWX823 156 25M 23 4 X3 Pin Receptical 1407 0 15 01 11 27 10 0 24 1 R35 178k 1 resistor SMD 0805 RC0805FR 07178KL 25 1 R54 301k...

Страница 42: ...CLK5406D 42 1 U2 3 3V fixed regulator SMD 8SOIC TPS77733D 43 1 U3 Adj LDO Regulator SMD 8SOIC TPS77701D 44 1 U4 74LVC3G34 Triple Buffer 8 SSOP SN74LVC3G34DCTR 45 4 N A 3M Rubber Bump ons P416 SJ 5003 46 1 N A 3M Static Bag 5X8 50F7150 47 2 N A Extra Nut for J11 J12 1 4 32 THR 1448 Table 3 Bill of Materials Continued Item Quantity Reference Part Part Number ...

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