20
ispClock5400D Evaluation Board
Lattice Semiconductor
User’s Guide
Set up the evaluation board for a phase jitter measurement:
1.
Set the evaluation board DIP switches to enable
3.3V VCCO
.
2.
Enable the
REFA
Oscillator input.
3.
Disable the
REFB
Oscillator input.
4.
Set the REF_SEL switch to
0
.
5.
Connect the BANK0 differential outputs to the SIA-3000D differential inputs.
6.
From the SIA-3000D GigaView software, execute
Pulse Find
.
7.
Initiate Clock Analysis measurement. Typical phase jitter for the ispClock5406D is 2.5ps.
SERDES Clock Source for LatticeECP3 Serial Protocol Board Demo
AN6081,
Driving SERDES Devices with the ispClock5400D Differential Clock Buffer
, describes the low-jitter perfor-
mance characteristics of the ispClock5406D clock output in the context of a XAUI application. SMA connections
J29, J33 and J30, J34 of the LatticeECP3 Serial Protocol Board allow you to connect the SMA outputs of the
ispClock5400D Evaluation Board as high-quality clock source.
Video Clock Source for LatticeECP3 Video Protocol Board Demo
AN6081,
Driving SERDES Devices with the ispClock5400D Differential Clock Buffer
, describes the low-jitter perfor-
mance characteristics of the ispClock5406D clock output in the context of a 270 MHz SDI video application.
This demonstration requires Lattice Intellectual Property for the LatticeECP3 FPGA. Please contact Lattice for
more information on how to obtain the project source.
Download Demo Designs
The ispClock5406D base demo is preprogrammed into the evaluation board, however over time it is likely your
board will be modified. Lattice distributes source and programming files for demonstration designs compatible with
the evaluation board.
To download demo designs:
1.
Browse to the
ispClock5400D Evaluation Board web page
of the Lattice web site. Select the
Demo Applica-
tions
download and save the file.
Extract the contents of Base_Demo_CLK5406.zip to an accessible location on your hard drive.
Export an ispClock5406D JEDEC with PAC-Designer
Use the procedure below to re-export a JEDEC programming file for any ispClock5406D demo project for the eval-
uation board.
1.
Install and license PAC-Designer software (
www.latticesemi.com/products/designsoftware/pacdesigner
).
2.
Download the demo source files from the ispClock5400D Evaluation Board web page.
3.
Run PAC-Designer.
4.
Open the
<demo>.pac
project file.
5.
Choose
File > Export…
The Export dialog appears.
6.
Select
Export What: Jedec File
.
