CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
126
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FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Table A. 13. Tx Pre-Cursor Ratio [reg0b]
Field
Name
Access
Width
Reset
Description
[7:0]
tx_pre_ratio
RW
8
8’h00
This register defines the Tx pre-cursor ratio for PCI Gen1
speed or non-PCIe protocols. A value of 8’d128
corresponds to 100% (full voltage) whereas a value of 8’d0
corresponds to 0%.
Note: This register can be reprogrammed during normal operation but effect only appears when the parameter for SerDes (PMA)
transmitter has been updated (at the end of calibration, on entry or exit of Tx electrical idle or when reg80 bit 1 has been
programmed).
Table A. 14. Power down Feature [reg0e]
Field
Name
Access
Width
Reset
Description
[7:6]
rxidle_msb
RW
2
2’b11
Used as the MSB bits of the activity detector logic,
enabling to specify that no activity is detected during up
to 61 TxClkp clock cycles. These bits are the 2 MSB bits
whereas the rxidle_max[3:0] field of reg02 represent the
LSB part.
[5]
force_signal
RW
1
1’b0
Disables the Idle detection circuitry and forces signal
detection on the receiver.
1’b1 – disabling.
1’b0 – normal operation.
[4]
force_idle
RW
1
1’b0
Disables the Idle detection circuitry and forces Electrical
Idle detection on the receive side.
1’b1 – disabling.
1’b0 – normal operation.
[3]
NO_FCMP
RW
1
1’b0
Disables the frequency comparator logic of the PCS-driven
CDR PLL control logic.
1’b1 – the frequency comparator logic is not any part of
the condition for going from fine-grain lock state to
frequency acquisition.
1’b0 – normal operation.
[2]
PMFF_ALL
RW
1
1’b0
Intended for disabling the function which waits for every
active lane to have valid data to transmit to generate a
global read enable.
1’b1 – each lane might start transmitting data with one
500 MHz clock uncertainty (corresponding to 5-bit or
10-bit time depending on the speed of the link).
1’b0 – normal operation.
[1]
CDR_ERR
RW
1
1’b0
Intended for internally disabling the error counter of the
CDR PLL state machine which switches back the CDR PLL
to frequency mode acquisition when the number of errors
counted is higher than the predefined error threshold.
1’b1 – disables the error counter.
1’b0 – normal operation.
[0]
CDR_P1
RW
1
1’b0
Defines the state of the CDR PLL when the PHY is in P1 low
power mode. Note that this bit must not be set for
application which removes reference clock in P1 mode.
1’b1 – the CDR PLL is kept alive in frequency lock mode
in P1 state which enables a faster recovery time from
P1 state, but which also consumes more power (all Rx
logic is kept alive and consume power in P1 state).
1’b0 – the CDR PLL is put in reset and low-power,
enabling to save maximum power.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is ready), except for
bit-2 which can only be modified under reset condition.
