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Lake Shore Model 480 Fluxmeter User’s Manual
6-4 Computer Interface Operation
Bus Control Commands (Continued)
Below are Status Byte Register bit assignments. These reports occur only if enabled in the Service
Request Enable Register.
Standard Event Status (ESB) Bit (5) – When set, indicates if one of the bits from the Standard
Event Status Register has been set. Refer to Paragraph 6.1.3.2.
Overload Indicator (OVI) Bit (4) – When set, indicates a display overload condition. Issues a
Service Request if enabled.
Auto Adjust Fail (AAF) Bit (3) – When set, the Auto adjustment has failed. This can occur if the
drift rate of the instrument is greater than what can be adjusted for. If this bit is set, then the AAC
bit will be set as well.
Alarm (ALM) Bit (2) – When set, an alarm condition exists. This condition latches until
acknowledged by the bus controller.
Auto Adjust Complete (AAC) Bit (1) – When set, the Auto Drift adjustment has been completed.
This bit will be set even if the Auto Drift adjustment fails. Refer to the AAF bit above.
Field Data Ready (FDR) Bit (0) – When set, new valid field readings are available.
6.1.3.2 Standard Event Status Register and Standard Event Status Enable Register
The Standard Event Status Register supplies various conditions of the Model 480.
STANDARD EVENT STATUS REGISTER FORMAT
Bit – 7 6 5 4 3 2 1 0
Weighting – 128 64 32 16 8 4 2 1
Bit Name – PON
Not Used
CME EXE DDE QYE
Not Used
OPC
Bits 2 and 6 are not used. Reports of this register interrupt the user only if the bits are enabled in
the Standard Event Status Enable Register and if bit 5 of the Service Request Enable Register is
set.
The Standard Event Status Enable Register allows the user to enable any of the Standard Event
Status Register reports. The Standard Event Status Enable command (
Q
ESE) sets the Standard
Event Status Enable Register bits. Setting a bit of this register, enables that function. To set a bit,
send the command
Q
ESE with the sum of the bit weighting for each bit to be set. Refer to the
Q
ESE
command.
The Standard Event Status Enable Query,
Q
ESE?, reads the Standard Event Status Enable
Register.
Q
ESR? reads the Standard Event Status Register. Once this register is read, the bits
reset to zero.
Power On (PON) Bit (7) – Set to indicate a controller off-on-off transition.
Command Error (CME) Bit (5) – Set to indicate a command error since the last reading. Controller
unable to interpret a command due to syntax error, unrecognized header or terminators, or
unsupported command.
Execution Error (EXE) Bit (4) – Set to indicate an execution error. This occurs when the controller
is instructed to do something not within its capabilities.
Device Dependent Error (DDE) Bit (3) – Set to indicate a device dependent error. Determine the
actual device dependent error by executing the various device dependent queries.
Query Error (QYE) Bit (2) – Set to indicate a query error. Occurs rarely, but involves data loss due
to full output queue.
Operation Complete (OPC) Bit (0) – This bit is generated in response to the
Q
OPC common
command. It indicates when the Model 480 has completed all selected pending operations.