Fig. 3-1. Illustration of the personnel principle for acquiring ADC data
3.3.3. Digital input channel.
Synchronous digital input occurs with a period of
t
ref
*
n
din
,
where
n
din
={1,2,…,2097152} is a configurable frequency division factor for synchronous
digital input.
3.3.4. Digital output and DAC channels
Synchronous digital output, as well as updating both channels of the DAC, occurs with a period
of 2*
t
ref
. If the data buffer for the output and the DAC is empty, then the last value is held at the
outputs.
With any DAC channel and digital output, you can work asynchronously, with the other
channels assigned as synchronous, the same synchronous mode is supported: either a streaming or an
self-oscillator from an internal buffer.
3.3.4.1. Restrictions on the current implementation of asynchronous output during
external synchronization.
Asynchronous output to digital lines and to DAC in the operating mode will always work when
configured for internal synchronization. But asynchronous output to digital lines and to the DAC will
not function in the standby mode for external synchronization of the start of data acquisition or
waiting for more than 1 μs of the external clock of the ADC conversion.
2
1
3
2
3
Канал 1
Канал 2
Канал 3
t
k
n
k
=3
t
d
t
k
t
ch
Кадр
Межкадровая
задержка
Кадр
Межкадровая
задержка
t
sw
1
Момент сэмплирования отсчётов данных АЦП
Номер
логического
канала АЦП
Sampling timing of ADC data
Logical
ADC
number
Channel 2
Channel 3
Channel 1
Interframe
delay
Interframe
delay
Frame
Frame
