SMARC-sAMX7 User Guide. Rev. 1.9
// 36
UART port mapping in DCE/DTE mode defines RTS_B and CTS_B in different manner as used in SMARC 2.0 spec. In
the following table the pin and signal direction are like in SMARC 2.0 spec.
Table 15: UART port mapping in DCE/DTE mode
IO Pads Name
DCE mode
DTE mode
UART function
IO direction
UART function
IO direction
UARTx_CTS#
RTS#
Output
SERx_CTS#
Input
UARTx_RTX#
CTS#
Input
SERx_RTS#
Output
UARTx_TXD
TX
Output
SERx_RX
Input
UARTx_RXD
RX
Input
SERx_TX
Output
Table 16: UART connections between CPU and SMARC 2.0 connector
CPU
Interface
CPU pins
Function
SMARC 2.0
connector
UART1
1
UART1_RXD/I2C1_SCL/L3
DTE_TX
I2C_LCD_SCL/S139
UART1_TXD/I2C1_SDA/L4
DTE_RX
I2C_LCD_SDA/S140
UART2
2
LCD_CLK/ECSPI4_MISO/UART2_R
XD/E20
DTE_TX
GPIO[7]/P115
LCD_ENABLE/ECSPI4_MOSI/UART
2_TXD/F25
DTE_RX
GPIO[8]/P116
UART3
UART3_RXD/GPIO4_IO04/M1
DTE_TX
GPIO[9]/P117
UART3_TXD/GPIO4_IO05/M2
DTE_RX
GPIO[10]/P118
UART4
SAI2_TXFS/UART4_RXD/D9
DTE_TX
SER[1]_TX/P134
SAI2_TXC/UART4_TXD/D8
DTE_RX
SER[1]_RX/P135
UART5
I2C4_SCL/UART5_RXD/L1
DTE_TX
SER[3]_TX/P140
I2C4_SDA/UART5_TXD/L2
DTE_RX
SER[3]_RX/P141
UART6
ECSPI1_SCLK/UART6_RXD/H3
DTE_TX
SER[0]_TX/P129
ECSPI1_MOSI/UART6_TXD/G5
DTE_RX
SER[0]_RX/P130
ECSPI1_MISO/UART6_RTS#/H4
DTE_RTS#
SER[0]_RTS#/P131
ECSPI_SS0/UART6_CTS#/H5
DTE_CTS#
SER[0]_CTS#/P132
UART7
ECSPI2_SCLK/UART7_RXD/J5
DTE_TX
SER[2]_TX/P136
ECSPI2_MOSI/UART7_TXD/G6
DTE_RX
SER[2]_RX/P137
ECSPI2_SS0/UART7_CTS#/J6
DTE_CTS#
SER[2]_CTS#/P139
ECSPI2_MISO/UART7_RTS#/H6
DTE_RTS#
SER[2]_RTS#/P138
1
Only usable if no I2C device is connected at I2C_LCD bus, therefore display converter has to be omit
2
Only usable if APPROTECT key does not use SPI (omit SPI level shifter TXB0104RUT) and stuffed additional
resistors