Kontron SBC-845D-VEA, Руководство пользователя

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SBC-845D-VEA Single Board Computer User’s Guide
This chipset settings deal with CPU access to dynamic random access memory (DRAM). The
default timings have been carefully chosen and should only be altered if data is being lost. Such
a scenario might well occur if your system had mixed speed DRAM chips installed so that greater
delays may be required to preserve the integrity of the data held in the slower memory chips.
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DRAM Time Selectable
This option provides DIMM Plug-andplay support by serial presence detect(SPD) mechanism via
the SMBUus interface.
The choice: Manual/ By SPD
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Masked: CAS Latency Time
This option controls the number of SCLKs between the time a read command is sampled by the
SDRAMs and the time the GMCH samples correspondent data from the SDRAMs.
The Choice: 1.5, 2, 2.5, 3 SCLKs.
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Masked: Active to Precharge Delay
This is to DDR standard accordingly.
The choice: 7, 6, 5
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Masked: DRAM RAS-to-CAS Delay
This option controls the number of SCLKs (SDRAM Clock) from a row activate command to a read
or write command. If your system installs good quality of SDRAM, you can set this option to “3
SCLKs” to obtain better memory performance. Normally, the option will be set to Auto.
The Choice: 2 or 3