Kontron ePCI-101, Руководство пользователя, Страница: 65 / 109

4-12
ePCI-101 User’s Guide
4.1.2.5.4 Advanced Chipset Control
Feature Options Description
Feature Set Display Only
Show witch Northbridge is selected to set some options to the
board.
DDR ECC operation
Enabled
Disabled
Control ECC enabling. If enabled, code will determine if DDR
support ECC before enabling ECC.
Watchdog Timer
Disabled
RESET
Enable the watchdog circuit when the POST is running.
Timeout
1 sec
5 sec
10 sec
30 sec
1 min
5.5 min
10.5 min
30.5 min
Maximum trigger period.
Delay
1 sec
5 sec
10 sec
30 sec
1 min
5.5 min
10.5 min
30.5 min
Time until watchdog timer starts to count.
Display and Clear
Reset History Enabled
Disabled When enabled, display in BIOS summary screen the type of reset
detected by the CPLD. The history bit in CPLD will also be cleared.
Clock Gen spread
spectrum
Enabled
Disabled
Control the spread spectrum feature of the clock generator. Allow
clock to be spread for EMI enhancement.
4.1.2.5.5 Cache Memory
You can make the following selections on the Cache Memory Sub-Menu.
Feature Options Description
Memory Cache
Enabled
Disabled
Sets the state of memory cache.
Cache System
BIOS area Uncached
Write Protect
Controls caching of system BIOS area.
Cache Video
BIOS area
Uncached
Write Protect
Controls caching of video BIOS area.
Cache Base
0-512K
Uncached
Write Through
Write Protect
Write Back
Controls caching of 512K base memory.
Cache Base
512K-640K
Uncached
Write Through
Write Protect
Write Back
Controls caching of 512K-640K base memory.
Cache Extended
Memory Area
Uncached
Write Through
Write Protect
Write Back
Controls caching of system memory above 1MB.