CP3005-SA – Rev. 0.6 Preliminary
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4.3.6.
Reset Status Register (RSTAT)
The Reset Status Register is used to determine the host’s reset source.
Table 18: Reset Status Register (RSTAT)
Address
0x285
Bit
7
6
5
4
3
2
1
0
Name
PORS
Reserved
R
0000
FPRS
CPRS
WTRS
Access
R/W
R/W
R/W
R/W
Reset
N/A
0
0
0
Bitfield
Description
7
PORS
Power-on reset status:
0 = System reset generated by warm reset
1 = System reset generated by power-on (cold) reset
Writing a ’1’ to this bit clears it.
2
FPRS
Front panel push button reset status (MMEXT05/MMEXT05-CMC02):
0 = System reset not generated by front panel reset
1 = System reset generated by front panel reset
Writing a ’1’ to this bit clears it.
1
CPRS
CompactPCI reset status (PRST signal):
0 = System reset not generated by CompactPCI reset input
1 = System reset generated by CompactPCI reset input
Writing a ’1’ to this bit clears it.
0
WTRS
Watchdog timer reset status:
0 = System reset not generated by Watchdog timer
1 = System reset generated by Watchdog timer
Writing a ’1’ to this bit clears it.
The Reset Status Register is set to default values by power-on (cold) reset, not by a warm
reset.
