Keysight ixia UHD100T32, Руководство по началу работы

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Feature Specifications
Transmit Line
Clock
Adjustment Ability to adjust the parts-per-million (ppm) line frequency over a range of +/-
100 ppm on all the ports of a 100GE fixed chassis system
Receive Feature Specifications
Receive Engine Wire-speed real-time latency and sequence checking capability
Trackable
Receive Flows
per Port (Max) 100GE: 1,000
50GE: 512
40GE: 1,000
25GE: 256
10GE: 256
Minimum Frame
Size 200 bytes at full line rate
Standard
Statistics and
Rates Link state, line speed, frames sent, valid frames received, bytes sent and
received, fragments, undersize, oversize, CRC errors, sequence checking frames,
sequence checking errors, ARP, and PING requests and replies
Latency and
Jitter
Measurements Store and forward
Layer 2-3 Protocol Support
Routing and
Switching BGP4/BGP4+, OSPFv2/v3, ISISv4/v6
Front Panel
Front Panel (100G Unit)
The UHD100T32 100GE High Density 32-port QSFP28 front panel image is as follows:
Chapter 1 About UHD100T32
913-2626-01 – 6 –