Keysight Technologies M8132A, Руководство пользователя

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Keysight M8132A 640 GSa/s Digital Signal Processor User’s Guide 59
Remote Programming 6
:CALibrate:LATency[:STEP]
Command
:CALibrate:LATency[:STEP] {GSYNc | ALIGnphase | SSYNc
| ARMadjust | PREPare}
Description This command executes a step in the latency calibration of the data path
between master and slave. As mentioned in brackets, some commands are
sent to and affect only the master and some only the slave module. It is
indicated as well, when commands are relevant only for one calibration
mode (SEParate, COMBined).
• GSYNc - Generate clock signal at Sync Out (master, SEParate).
• ALIGnphase - Use the clock signal received at Sync In to align the
phase of the core clock (slave).
• SSYNc - Stop the clock signal generation at Sync Out (master).
• ARMadjust - Arm the module for latency adjustment (slave). When the
master starts sending data over the ODI, the latency is measured in the
slave, and the FIFOs are adjusted accordingly.
• PREPare - Set the Sync Out to pulse mode (master, SEParate). When
data streaming is started, a single pulse is sent at the Sync Out.
:CALibrate:LATency:SPDelay
Command
:CALibrate:LATency:SPDelay {A|B}, <sync_pulse_delay>
Description This command sets the synchronization pulse delay for the selected FPGA
in multiples of the core clock period (5ns).
A Selects FPGA A.
B Selects FPGA B.
<sync_pulse_delay> The synchronization pulse delay as an unsigned
integer between 0 and 1023.
Query
:CALibrate:LATency:SPDelay? {A|B}
Description This query returns the synchronization pulse delay for the selected FPGA.