TS-5700
CIRCU IT D ES CRI PTI O N
•
DDS Circu it Confi g u ration
The DDS IC has been developed with standard cells
to implement a high-speed operation circuit and large
capacity ROM at a low cost.
1 )
IC config u ration
The IC consists of the following components
Two 28 bit registers for setting frequency data, one
28 bit frequency shift register for addition to the fre
quency register, a 23 bit parallel signal input section
for frequency modulation with a parallel signal, and a
data entry and selection section.
Frequency modulation section comprised of a 28
bit adder that adds frequency data and frequency
modulation data
Phase data operation section that adds data from
the frequency modulation section with the 28 bit
phase data register
SIN-ROM that converts phase data to sine data.
2)
Frequency/sh ift data setti n g
Using serial signals synchronized with clock pulses,
a total of 30 bits (2 bits that specify the destination to
which data are set and 28 bits for frequency data) are
set in three internal registers.
3) Frequ ency reg ister selection
The data set in the two frequency registers are se
lected by the SLAB input of the DDS IC. This pin
handles the TXC signal. This function eliminates the
need for the TS-570D microprocessor to set fre
quency data for each transmission and reception.
4) Frequency data selection
The SPSL input of the DDS IC selects whether to
use the data in the internal frequency shift register or
the data from parallel input as frequency modulation
data.
5) Frequency modulation
The MOEN input of the DDS IC enables or disables
frequency modulation. When frequency modulation is
enabled, frequency data is added, and the result is
input to the phase data operation section.
6)
Phase data operation
The target frequency phase data is output by accu
mulating 28 bit frequency data in the 28 bit phase ac
cumulator.
Fout
=
Fs/228
·
Dsum
Fs : DDS IC input frequency/2
Dsum : Frequency data+Frequency modulation
data
If 225 is set for Dsum when 1 /8 Fs is output, the
phase data must be increased by n/8.
A 28 bit absolute value operation has been used
here, but a 28 bit signed operation can also be used,
assuming that the MSB is a sign. If complement data
of 8000000 to FFFFFFFF (hex) is set, the phase moves
in the negative direction for the positive data.
71
SIN-ROM
Phase data from the phase data operation section is
converted to sine data of 0000 to FFFF (hex) in the 1 6
bit offset binary format.
2n=22B
71t/8=-225
Fig. 3
5
