TS-5700
S E M I CO N D U CTOR DATA
Pin
Name
Port
1/0
Details
45
cs
I
46-48
IAD8 - IA D 1 0
AO-A2
1/0
Pseudo bus
49
no
P E O
0
Exte r n a l AT control
" H "
: AT t h ro u g h req u e st, " L" : Others
50
TSO
P E l
0
Exte r n a l AT control
" H "
: AT t u n i n g requ est. " L" : Others
5 1
N C
52
TSI
PE2
I
Exte r n a l AT control
" H "
: AT t h r o u g h e n d , " L" : Others
53
TTI
PE3
I
Exte r n a l AT control
" H "
: AT t u n i n g e n d , " L" :
Others
54 - 5 6
TY P E O - TY P E 2
PAO - PA2
I
Destination
U n it destination sett i n g
5 7
Vss
G N D
58
Vdd
5V
59,60
TYP E 3 , TYPE4
PA3 , PA4
I
Destination
U n it desti nation sett i n g
6 1
TY P E 5
PA5
I
Dest i nation
U n it destination sett i n g ( R eserve)
62
TY P E 6
PA6
I
Dest i nation
" L" : 50MHz band i nsta l l e d , " H " : 50 M H z band not i nsta l led
63
TY P E 7
PA7
I
Desti nation
U n it destination sett i n g ( R eserve)
64
F E N
P B O
0
E n a b l e
" H " :
FFA u n it seria l/para l lel reg ister throu gh, " L" : FFA u n it seria l/para l l e l reg ister latch
Decoder : NJU37 1 4G ( F i n a l U nit IC6)
•
Term i n a l con n ection diagram
•
Block diagram
P 5
1
20
VDD
DATA
P6
2
1 9
P4
P7
3
1 8
P3
CLK
PB
4
1 7
P2
a:
f-
Vss
5
1 6
P 1
w
s
f-
(/)
u
6
1 5
Vss
(5
a:
w
u
CLR
P 1 0
7
1 4
a:
I
f-
u
P 1 1
8
1 3
STB
LL
f-
I
<t
P 1 2
9
1 2
CLK
(/)
_J
so
1 0
1 1
DATA
STB
CLR
CONTOROL CIRCUIT
Clock Divider : TC74HC4040AF (Control U n it IC508)
•
Term i n a l connection diagram
0 1 2
Vee
06
0 1 1
05
0 1 0
Q7
08
04
09
03
CLR
02
CK
G N D
0 1
P 1
P2
P3
P4
P5
P 1 1
P 1 2
37