TK-3202
8
3. PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
■
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz.
A 12.8MHz reference oscillator signal is divided at IC1 by a
fixed counter to produce an oscillator (VCO) output signal
which is buffer amplified by Q2 then divided in IC1 by a pro-
grammable counter. The divided signal is compared in phase
with the 5 or 6.25kHz reference signal from the phase com-
parator in IC1. The output signal from the phase comparator
is filtered through a low-pass filter and passed to the VCO to
control the oscillator frequency. (See Fig. 5)
■
VCO
The operating frequency is generated by Q4 in transmit
mode and Q3 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D4 and
D7 in transmit mode and D5 and D9 in receive mode). The RX
pin is set high in receive mode causing Q5 turn on.
The TX pin is set high in transmit mode. The outputs from
Q3 and Q4 are amplified by Q6 and sent to the RF amplifiers.
■
Unlock Detector
If a pulse signal appears at the LD pin of IC1, an unlock
condition occurs, and the DC voltage obtained from C4, R5
and D1 causes the voltage applied to the microprocessor to
go low. When the microprocessor detects this condition, the
transmitter is disabled, ignoring the push-to-talk switch input
signal.
4. Transmitter System
■
Microphone Amplifier
The signal from the microphone passes through the
IC301. When encoding DTMF, it is turned OFF for muting
the microphone input signal by IC301.
The signal passes through the Audio processor (IC301) for
the maximum deviation adjustment, and goes to the VCO
modulation input.
D4,7
Q4
TX VCO
D5,9
Q3
RX VCO
Q6
BUFF AMP
Q9
RF AMP
Q2
BUFFER
LPF
LPF
Q5,7
T/R SW
RX
TX
REF OSC
1/M
1/N
Phase
comparator
Charge
pump
5kHz/6.25kHz
5kHz/6.25kHz
PLL DATA
X1
12.8MHz
IC1
PLL IC
Fig. 5
PLL circuit
AGC
LPF
LPF
VCO
LPF
TCXO
MIC
DTMF
IC301
AQUA-L
IC405
CPU
QTVCO
QTTCXO
X1
Fig. 6
Microphone amplifier
■
Drive and Final Amplifier
The signal from the T/R switch (D101 is on) is amplified by
the pre-drive (Q101) and the drive amplifier (Q102) to 50mW.
The output of the drive amplifier is amplified by the TX
fianl amplifier (Q103) to 4.0W (1W when the power is low).
The RF power amplifier consists of two MOS FET stages.
The output of the RF power amplifier is then passed through
the harmonic filter (LPF) and antenna switch (D103 and D122)
and applied to the antenna terminal.
■
APC Circuit
The APC circuit always monitors the current flowing
through the TX fianl amplifier (Q103) and keeps a constant
current. The voltage drop at R127, R128 and R129 is caused
by the current flowing through the TX fianl amplifier and this
voltage is applied to the differential amplifier IC101 (1/2).
IC101 (2/2) compares the output voltage of IC101 (1/2)
with the reference voltage from IC405. The output of IC101
(2/2) controls the VG of the TX fianl amplifier, drive amplifier
and pre-drive amplifier to make both voltages the same.
The change of power high/low is carried out by the change
of the reference voltage.
From
T/R SW
(D101)
Drive
AMP
Pre-drive
AMP
Q101
Q102
RF
AMP
Q100
TX final
AMP
Q103
ANT
SW
LPF
D103,122
ANT
VDD
VG
IC101
(1/2)
IC101
(2/2)
R127
R128
R129
+B
PCTV
(IC405)
5T
5T
VD
VG
VG
Fig. 7
Drive and Final amplifier and APC circuit
CIRCUIT DESCR
I
PTION
