TH-K2AT/K2E/K2ET
9
CIRCUIT DESCRIPTION
The APC voltage controls the gate voltage of Q11 and Q12,
and keeps transmission output stable.
The M PU detects pow er supply voltage and controls Q58
by transmission pow er supply voltage and transmission pow er.
For example, if the pow er supply voltage during transmission,
is equal to or higher than approx. 10.5 V and if pow er is at M id
or Low level, the APC voltage level applied to Q12 is reduced
by Q58.
■
Temperature Protection Circuit
To prevent thermal destruction of the pow er amplifier (Q12),
this circuit reduces APC voltage w hen Q12 temperature rises.
The M PU (IC8) detects temperature w ith a thermistor (TH1)
and controls reference voltage to the APC circuit.
PLL System
■
PLL Circuit
A reference frequency of 5 kHz or 6.25 kHz is produced by
dividing the 12.8 M Hz reference frequency of the TCXO (X1)
w ith PLL IC (IC1). Comparison frequency is produced by
TCXO
PLL IC
IC1
LOOP
FILTER
TO
TCXO
5C
5/0V
5M S
5/0V
PLL
5C
5/0V
VC
X1
12.8M Hz
CLOCK
DATA
LE
Fo/LD
IF
Rectifier
LPF
Q6
RF
Am p
D1,D2
VCO
5C
5/0V
LV
1~5V
SHIFT
H/L
Ripple
Filter
Q4
OSC
Q1
Buff
Am p
Q2
RF
Am p
Q5
SW
D8,D9
M OD
SHIFT
SW
Q3
M OD
12.8M Hz
TX
RX
5T 5/0V
5R 5/0V
VR
1
Fig. 8 PLL and VCO circuit
amplifying VCO output w ith an RF amplifier (Q6) and dividing
it w ith the PLL IC.
The PLL synthesizer w ith 5 kHz and 6.25 kHz step is
configured by comparing phases of the reference frequency
and comparison frequency.
The phase difference betw een reference frequency and
comparison frequency passes through a charge pump in the
PLL IC, then ripples are removed w ith a loop filter w ith low -
range passing characteristics to produce VCO control voltage
(lock voltage).
■
VCO Circuit
The VCO produces a desired frequency directly w ith a
Colpits oscillation circuit containing an oscillation transistor (Q1)
used for both transmission and reception.
The VCO control voltage is applied to varicap (D1, D2) to
produce a desired frequency.
The SHIFT terminal (pin 113) of the M PU (IC8) goes "H"
during reception, and the shift control sw itch (Q3) is turned
ON to change oscillation frequency.
Fo/LD
PLL LD
IC8
M PU
IC1
PLL IC
R32
D16
C40
R35
14
102
5C
Fig. 9 Unlock detection circuit
■
Unlock Detection Circuit
When the PLL is unlocked, the w aveform of the pulse
output from the Fo/LD terminal (pin 14) of the PLL IC (IC1) is
rectified w ith R32, D16, R35 and C40, and the Fo/LD terminal
is m ade “ L” level. The voltage at the Fo/LD term inal is
det ect ed by t he M PU t o cont rol t ransm ission/recept ion
sw itching timing.
