TS-440S
CIRCU IT D ESCRI PTION
into pin 2 of MIX 5 IC7 (SN 1 69 1 3P) via the L PF . In M IX 5,
the sig nal is mixed with the sig n a l generated by PLL4 and
goes through the B PF to generate a sig nal in the range of
6 . 5 3 MHz to 6.630 1 MHz (in 1 00 Hz steps). The gener
ated sig nal is supplied to pin 5 .
•
PLL2
PLL2 con sists of IC9 (MN6 1 47) and its loop circuitry .
VC02, 0 1 8 (2SC2668), is locked in the ra nge of 5 8 . 2 5
MHz t o 5 3 . 2 50 1 MHz . The 9 MHz reference frequency
signal is supplied to pin 3 of IC9, where the signal is divided
by 450 to generate a 20 kHz sig n a l for frequency com
pariso n . VC02's output goes through buffer amplifier 0 1 9
(2SC2668), and is fed into MIX4 pin 2 and mixed with
the 6 . 3 5 MHz to 6.63 MHz signals ap plied to pin 5 . The
mixed si� nal then goes through the BPF to obtain 64. 78
MHz to 59 . 88 MHz signal (in
1 00
kHz steps) . The
64.
78 MHz to 59.88 MHz signal is fed into IC9_ pin 1 6 via
buffer amplifier 0 1 5 (2SC2668) . In IC9, the signal is divided
by M, and the phase of signal is compared with that of the
20 kHz reference signal by the phase comparator, and thus
MIX4 output is locked (in
1 00
kHz step) . The division ratio M
is supplied from the digital unit (DAO to DA3 and
C K 1
), and is
in 50 steps from 3239 to
2994
corresponding to
0 . 00
MHz to
0 . 49
MHz.
The output from PLL2 goes throu g h buffer amplifier 020
(2SC2668) and is divided by ten in IC 1 0 (M54460L) . Via
the LPF, the signal is fed into pin 2 of M IX 3 IC 1 1
(SN 1 69 1 3P). The frequency of the signals depends on the
values of L a n d M, and is in the range of 5 . 8 2 5 MHz to
5 . 3 2 50 1 MHz ( 1 0 Hz step).
VR 1 in MIX4 circuit is used to suppress spurious outputs
from the mixer . It is necessary to prevent PLL2 from be
coming u n l ocked .
Signals generated by PLL2 and the 9 MHz reference fre
quency are mixed in MIX 3 . The mixed signal goes through
the BPF, and is further mixed with fLo in MIX 2 IC 1 2
(SN 1 69 1 3P) on the IF unit. The output from MIX 2 goes
through the B PF to obtain 38. 5 5 MHz to 39. 04999 MHz .
The sig nals a re then mixed with the output from the final
VCO oscillator in MIX 1 .
•
PLL 1
The last PLL loop, PLL 1 , consists of IC 1 7 (MB 87006) and
its loop components . In IC 1 7, frequency division for refer
ence and comarison frequencies is set by serial data (SO,
SCK, and LE). When a n external prescaler is used, IC 1 7
has a mod u l u s control function for config u ring the pulse
swallow cou nter.
The VCO oscil lator output from the RF u nit goes through
0 26 (2SC2668) in the PLL u nit and is fed into MIX 1 . The
mixed sig nals go through the BPF, and they are the n am
plified by buffer amplifie rs 027 thru 030 (2SC 2668),
shaped by IC 1 5 (SN74S 1 0N 1 /3), and fed into IC 1 6
(WN74S 1 1 2N) 1 /3, o r 1 /2 prescaler. Basical ly, IC 1 6 is a
two-level FF circuit and functions as a 1 /4 divider. But,
when IC 1 7 of the PLL u nit sends control sig n als, to IC 1 6,
IC 1 6 functions as a 1 /3 or 1 /2 frequency divider in con
junction with IC 1 5 (2/3) . That is, the IC 1 5, IC 1 6, and IC 1 7
form a pulse swallow frequency divide r .
The 9 MHz reference frequency sig n a l i s supplied to pin
1 of IC 1 7, where the sig nals a re divided by 1 8 to gener
ate a 500 kHz sig nal for freq uency compa rison . Signals
fed into IC 17 pin 8 via M IX 1 and the buffer amplifier a re
divided by N, and the phase is compared with that of the
500 kHz reference signals by the phase compa rator . The
sig nal then goes through the active LPFs 03 1 to 033
(2SC 2459) and is fed into the RF u nit as VCO voltage sig
nals to control the variable capacitor of the final VCO . The
frequency divider N covers the full range of operating fre
quencies from 30 kHz to 30 MHz ( 500 kHz step), and it
has 6 1 steps of frequency division data supplied by the
microprocessor in the digital u nit .
The l ast VCO sig nal in PLL 1 therefore depends on the
values of L, M, and N, and it is in the range from 4 5 . 08
MHz to 7 5 . 0 5 MHz ( 1 0 Hz step). N is expressed as
follows :
N = PNo -A
(No > A)
P :
Prescaler mod u l e value
No : Prog rammable cou nter value
A:
Swallow counte r value
PLL IC contains No and A .
The last VCO u nit is contained i n the RF u nit and consists
of four VC Os, each hand ling one portion of frequencies
from 30 kHz to 30 MHz . The appropriate VCO is selected
by the microprocessor according to band information from
the digital u nit .
•
Unlock
If a PLL loop enters a u n lock state, the output on the U L
pin becomes L . This L signal i s sent t o the digital u nit to
stop the microprocessor.
•
500 kHz marker signal
The 500 kHz reference sig nal for frequency compa rison
is supplied from IC 17 pin 1 3, and it is used as the marker
reference sig n a l .
5 .
Digital control circuit
The TS -440 digital control circuit uses an 8-bit CPU (7800)
which does not contain RO M, and has a 1 6K RO M (27 1 2 8)
and a 2K RA M (84 1 8) outside the CPU . A common bus used
for data exchange between the CPU and RA M, and between
the CPU and RO M and is also connected in parallel to the
two 8 2 5 5 's for extended 1/0 and an 8 2 5 1 for interface to
a personal computer (option). To transf�ata to...Q!:_ from an
appropriate IC, the CPU uses the WR or RD signal,
and the chip select sign a l from the 74LS 1 38 .
The display i s dynamica l ly controlled by softwa re, a n d con
sists of 1 3 digits and nine segments. The 1 3 digit and seven
segment sig nal is d riven by the high voltage resistive buffer
(6300), a n d the other two segment signals a re d riven by a
transistor . The 7800 transfers data serially. The clock sig nal
is frequency divided by two in the 40 1 3 and sent to the 6300.
U sing the 40 1 1 and 4030, the encoder generates count
1 7
