TS-440S
16
CIRCUIT D ESCRIPTION
VCO I A : 45.08-.,. 52.55 MH1
B : 52.55
,._
59.55 MHz
C : 59.55,..... 67.05MHz
3239..., 2994 !STEP 5
l
HET
fHET
I
I
I
I
I
CAR
L
9MHz
RIT(-120..., +120)
19800- 20799
L----
(
18260: use,cw
)
18140: LSB,FSK
IF SHIFT (-40- 401
CAR
(-16 .... 151
f CAR
USB,CW
)
LSB,FSK
Fig . 1 2 PLL circuit block diagram
•
PLL4
PLL4 consists of IC 1 (MN6 1 4 7) and its associated loop
circu it. VC 04, Q3 (2SC 2668), is locked at a frequency
of a proximately 9 1 MHz, which d iffe rs depending on the
operational mod e . The 9 MHz reference frequency is a p
plied to pin 3 of IC 1 , where the signal is divided by 1 800
to generated the 5 kHz signal for frequency comparison .
The output of V C 04 is supplied to IC 1 pin 1 6 via buffer
amplifier Q4 (2SC 2668). In IC 1 , the output is divided by
an appropriate division ratio ( 1 8200 or so) which d iffers
depending on the mod e . The phase of the signal is com
pared with that of the 5 kHz reference signal by the phase
comparator and the VC04 oscillation frequency is locked .
F requency d ivision d ata is sent from the digital u nit (DAO
to DA 3 and CK3).
The output from PLL4 goes through buffer amplifier Q 5
(2SC 2668) a n d is divided b y 20 i n IC 2 (M 544 59L). The
signal is fu rthe r divided by ten in the ca rrier circuit of IC 3
(SN74LS90N) and then fed i nto the IF u nit as the carrier
signal via the LPF, and buffer Q7 (2SC 24 5 8) and Q8
(2SC 1 9 59). In AM o r F M receive mode, switching circuit
Q6 (2SC 24 5 8) operates when a n SFT signal is sent, and
as a result, IC 3, Q7, and Q8 a re stopped to cut carrier
sig nals.
The PLL4 output signal also goes through the LPF and
buffer amplifier Q9 (2SC 2458) and is fed i nto the mixer
in the main loop, where the signal is used to form the d i g
ital VFO signal. As a resu lt, the operating frequency does
not change even if the carrier frequency is changed, which
enables USB and LSB mod e switching
IF
shift and fine car-
rier point adjustment. In SSB, CW, or FSK reception mode,
the may be shifted
+I
- 1 kHz or more and the carrier
point can be adjusted in the range from - 400 Hz to
+
3 50
Hz.
•
PLL3
PLL3 consists of IC4 (MN6 1 47) and its associated loop
components . VC03, Q 1 2 (2SC 2668), is locked in the
range of 99 MHz to 1 03 .99 5 MHz . The 9 MHz reference
frequency signal is supplied to pin 3 of IC4, where the sig
nal is divided by 1 800 to generate the 5 kHz signal for
frequency compa rison. The output of VC03 goes through
buffer amplifier Q 1 3 (2SC 2668) and is applied to IC4 pin
1 6 . In IC4, the output is divided by L and the phase of
the signal is compa red with that of the 5 kHz reference
signal by the frequency comparator, and VC03 oscillation
frequency is locked (in 5 kHz steps) . The d i vision ratio,
L, is suppl ied by the microprocessor, in the digital u nit,
(DAO to DA 3 and CK2). L is i n 1 000 steps ( 1 9800 to
20799) corresponding to 0 . 00 kHz to 9.99 kHz. In CW
receive, i n order to obtain 800 Hz beat signals in the oper
ation frequency display, the L is shifted - 80 ( 1 9720 to
207 1 9) and when RIT/X IT operates, the L is changed so
that fvco is shifted
+
/- 1 . 2 kHz or more . In AM or F M
mode, the L i s shifted by 1 0 steps t o change fvco by 1 00
Hz steps.
Output from PLL 3 goes through buffer ampl ifier Q 1 4
(2SC 2668) a n d it is divided by ten in IC 5 (M 54460L) and
then by five in IC6 (SN74LS90N). The signal is then fed
