JS-440S
CIRCUIT DESCRIPTION
4) Speech processor
IC4 in the IF u nit functions as the first stage microphone am
plifier or audio speech processor. When the processor switch
is off, IC 4 functions as a 20 dB microphone amplifier. When
the processor switch is on, IC 4 functions as an u p to 40 d B
g ain amplifier with A LC . When the processor switch is on,
8 VDC is supplied to the base of the g ain adjustment switch
ing transistor, 04 1 , d riving the feed back amp lifier.
PROCESSOR
OFF G AIN 20dB
0 N
MAX GAIN 40dB
IF UNIT
IC4: JJPC1158H2
MIC
COMP.
041 DTCI 14ES
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I
I
I
...
ALC
Fig . 1 1
SSB
M
IC GAIN
V R6
P RS BV
4. PLL
Circuits
•
PLL5
Theory of PLL circuit operations
The TS-440 PLL circuit uses a reference frequency of 36 MHz
and consists of five PLL loops covering the range of freq uen
cies from 30 kHz to 30 MHz in 1 0 Hz steps. The PLL circuit
has an IF shift function which is implemented by inserting
carrier frequencies between PLL loops . The PLL loops include
a carrier circuit PLL loop and a n HET circuit PLL loop which
generates a constant frequency of 36. 22 MHz . Frequency
division for these PLL loops is controlled by the microproces
sor. In all PLL loops phase comparison is made using the refer
ence frequency fsrn (frequency control using a single crystal
oscillator) .
Fig u re 1 2 i s the P L L circuit block diagram.
The reference frequency (fsrn) is generated by a 36 MHz
crystal oscillator and 02 1 (2SC 2787). Reference freq uency
sign als a re fed into the main loop ' s IC 1 1 (SN 1 69 1 3P) via a
buffer consisting 022 and 023 (2SC 2668). The signal is also
fed into IC 1 3 (S N74S 1 1 2) via a buffer consisting of 024
(2SC 2668). In IC 1 3, the sign als a re frequency divided to
generate a 9 MHz sig nal. The 9 MHz sig nal is used as the
reference frequency sig nals for the PLL loops .
PLL5 consists of IC 1 8 (MN6 1 4 7) and its associated loop
components . VC 0 5,036 (2SK 1 92A), is locked at a fre
quency of 36 . 2 2 MHz . The 9 MHz reference frequency
signal is supplied to pin 3 of IC 1 8, where the signal is divid
ed by 1 800 (450 in FM mode) to gene rate
a 5
kHz ( 2 0
kHz in F M mode) signal u s e d f o r comparison . VC0 5' s out
put sig nal is supplied to IC 1 8 pin 1 6 via 037 ( 2SC 2668),
where the sig n als are frequency divided by 7244 ( 1 8 1 1
in F M mode). The phase of the signal is then compared
with that of the 5 kHz (20 kHz in F M mode) sig nal by the
phase comparator and the VC 0 5 oscillation frequency is
locked . Frequency division d ata is supplied by digital u nit
(DAO to D A 3 and C K 4) .
As described a bove, the dividing ratio used varies depend
ing on which mode the TS -440 is in, FM mode or SS B .
This is because the apparent time constant is increased
without chan ging the active LPF constant so that the PLL
sig n als can be mod ulated easily and reducing distortion
d u ring F M transmission . In modes other tha n F M, the
amount of frequency shift due to mechanical vibrations
is reduced because the apparent time constant is reduced .
The output from PLL5 goes through buffer 038 (2SC 2668)
and LPFs, and is used as the HET signal in the R F u nit.
1 5
