4-4
External Interrupts
KPCI-3160 User’s Manual
Table 4-2
External-interrupt responses
Result
Interrupt Control/Status
Register
Interrupt Control Bits
(x = don’t care)
Port Group
Control Register
(x = don’t care)
External Inputs at
P101
Interrupt Control/
Status Register
Status after Edge
Transition*
INT Enable
Bit 12
Polarity
Bit 6
Bit 6
Bit 5
Enable
Pin 25
Edge
Pin 24
Polarity Bit 17
PCI-INT; No Latch
1
0
x
0
0
↑
1
PCI-INT; No Latch
1
1
x
0
0
↓
1
No PCI-INT; No Latch
(Programmed I/O Mode)
0
x
x
0
0
↑
or
↓
0
No PCI-INT; Latch Input Data
0
x
0
1
0
↑
1
No PCI-INT; No Latch
0
x
0
1
0
↓
0
No PCI-INT; No Latch
0
x
1
1
0
↑
0
No PCI-INT; Latch Input Data
0
x
1
1
0
↓
1
No PCI-INT; No Latch
(Programmed I/O Mode)
x
x
x
x
1
↑
or
↓
0
PCI-INT; Latch Input Data
1
0
0
1
0
↑
1
No PCI-INT; Latch Input Data
1
1
0
1
0
↑
1
No PCI-INT; No Latch
1
0
0
1
0
↓
0
PCI-INT; No Latch
1
1
0
1
0
↓
1
PCI-INT; No Latch
1
0
1
1
0
↑
1
No PCI-INT; No Latch
1
1
1
1
0
↑
0
No PCI-INT; Latch Input Data
1
0
1
1
0
↓
1
PCI-INT; Latch Input Data
1
1
1
1
0
↓
1
*For bit 17, assume an initial clear state before edge.
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Содержание KPCI-3160
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