B-6
I/O Address Mapping
KPCI-3160 User’s Manual
Interrupt example scenario
The following example is one possible scenario that may help you to understand and use the
KPCI-3160 interrupt feature. (This example is simplified, and some details may not apply to
your specific system or to your requirements.) It illustrates the workings of the interrupts and
bits 6, 12, 17, and 23 of the interrupt control/status register. (Refer also to
Section 4
, “
External
Interrupts
.”)
1. At some point, computer software sets interrupt-enable bit 12 of the interrupt control/status
register to logic-high. (The term “software” here refers to the combination of the application
programming interface (API)/driver—normally, DriverLINX—and the application program.
To understand how to program interrupt-triggered data acquisition through DriverLINX,
refer to your DriverLINX documentation.) This status, detected by board firmware, enables
the board to process data using external interrupts. It changes general-purpose inputs PC6
and PC7 of port group 3 into external interrupt request and external interrupt enable inputs
INT_REQ and INT_ENN.
2. At some point, computer software sets latching polarity bit 6 for port group 0 to determine
whether that data at port group 0 latches on the rising or falling edge of INT_REQ. This
action is repeated for port groups 1, 2, and 3.
3. Prior to sending data, a user circuit sets INT_ENN to logic low. Board firmware detects that
INT_ENN is low and allows the edges of interrupt signals at INT_REQ to be detected.
4. When data is ready to be transferred and processed, the user circuit sends an external inter-
rupt request signal to INT_REQ.
5. Board firmware detects the rising or falling edge of the INT_REQ signal, depending on
interrupt polarity settings in the port-group control registers (
Table B-2
).
6. Software sets bit 6 of the interrupt control/status register high or low depending on whether
the user wants a PCI interrupt to be triggered by the falling or rising edge of INT_REQ.
7. If inputs are configured to latch, board firmware latches these input ports. (See bits 5 and 6 in
Table B-2
.)
8. The interrupt-received status in board firmware causes interrupt-pending bit 17 of the inter-
rupt control/status register to be set to logic high.
9. The interrupt-received status in board firmware causes a computer CPU interrupt to start,
stopping execution of the current CPU task.
10. Computer hardware detects an interrupt request signal and transfers control to an interrupt
service routine (ISR).
11. Computer software starts the ISR, which takes control of the CPU and starts processing the
KPCI-3160 input data.
12. The ISR proceeds.
13. Ideally, for a well-planned data acquisition session, both of the following conditions are met
while the ISR is in progress and the interrupt-pending bit is set:
•
No new external interrupt requests occur during this time.
•
If the board is set to detect both the rising and falling edges of an interrupt request signal,
AND the rising edge started the ISR, then the falling edge does not occur during this
time.
However if either or both of the above conditions are not met while the interrupt-pending bit
is set, the following occurs:
a. The rising and/or falling edges of interrupt signals have no effect; these interrupts are
missed.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
Содержание KPCI-3160
Страница 12: ...1 Overview Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...
Страница 18: ...3 Installation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...
Страница 40: ...5 Troubleshooting Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...
Страница 68: ...A Specifications Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...
Страница 81: ...C Glossary Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...