Keithley KPCI-3110, Руководство пользователя

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2-8 Functional Description KPCI-3110 and KPCI-3116 User’s Manual
Continuously-paced scan mode (rate generation: internal clock)
Use continuously-paced scan mode if you want to accurately control the period between conver-
sions of individual channels in a scan.
When it detects an initial trigger, the board cycles through the channel-gain list, acquiring and
converting the value for each entry in the channel list. This process is defined as the scan. The
board then wraps to the start of the channel-gain list and repeats the process continuously until
either the specified samples are taken or you stop the operation. Refer to
page 2-15 for more
information on buffers.
The conversion rate is determined by the frequency of the A/D sample clock. Refer to page 2-6
for more information on the A/D sample clock. The sample rate, which is the rate at which a sin-
gle entry in the channel-gain list is sampled, is determined by the frequency of the A/D sample
clock divided by the number of entries in the channel-gain list.
NOTE
An A/D Trigger Out signal is provided for your use. This signal is high
when the A/D subsystem is waiting for a trigger and low when a trigger
occurs. In continuously-paced scan mode, this signal goes low when the
trigger occurs and stays low until you stop the operation.
Triggered scan mode
KPCI-3110 and KPCI-3116 boards support two triggered scan (burst) modes: internally-clocked
and externally-clocked. These modes are described in the following subsections.
Internally-retriggered scan mode (internal clock: burst mode)
Use internally-retriggered scan mode if you want to accurately control both the period between
conversions of individual channels in a scan and the period between each scan. This mode is
useful when synchronizing or controlling external equipment, or when acquiring a buffer of data
on each trigger or retrigger. Using this mode, you can acquire up to 262,144 samples per trigger
(256 times per trigger x 1024-location channel-gain list).
When it detects an initial trigger, the board scans the channel-gain list a specified number of
times (up to 256), then waits for an internal retrigger to occur. When the board detects an inter-
nal retrigger, the board scans the channel-gain list the specified number of times, then waits for
another internal retrigger to occur. The process repeats continuously until either the specified
samples are taken or you stop the operation.
The sample rate is determined by the frequency of the A/D sample clock divided by the number
of entries in the channel-gain list. Refer to
page 2-6 for more information on the A/D sample
clock. The conversion rate of each scan is determined by the frequency of the internal retrigger
clock. The internal retrigger clock is the Triggered Scan Counter, a 24-bit counter with a 20MHz
clock located on the board.
Using DriverLINX software, specify the frequency of the internal retrigger clock. The minimum
retrigger frequency is 1.2Hz. For KPCI-3110 boards, the maximum retrigger frequency is
357.14kHz (357.14 kSamples/s); for KPCI-3116 boards, the maximum retrigger frequency is
166.67kHz (166.666 kSamples/s).