Keithley KPCI-3101 Series, Руководство пользователя

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List of Illustrations
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2 Principles of Operation
Figure 2-1 Block diagram of the KPCI-3101–4 series boards...................................................................................... 2-2
Figure 2-2 Continuous post-trigger mode without triggered scan .............................................................................. 2-11
Figure 2-3 Continuous post-trigger mode with triggered scan ................................................................................... 2-11
Figure 2-4 Continuous pre-trigger mode .................................................................................................................... 2-12
Figure 2-5 Continuous pre-trigger mode with triggered scan..................................................................................... 2-12
Figure 2-6 Continuous about-trigger mode ................................................................................................................ 2-13
Figure 2-7 Continuous about-trigger mode with triggered scan................................................................................ 2-14
Figure 2-8 Counter/Timer channel ............................................................................................................................ 2-19
Figure 2-9 Example of a Low-to-High pulse output type........................................................................................... 2-22
Figure 2-10 Connecting event counting signals (shown for clock input 0 and external gate 0)................................... 2-23
Figure 2-11 Example of event counting ....................................................................................................................... 2-24
Figure 2-12 Connecting frequency measurement signals without an external gate input (shown for clock input 0) .. 2-24
Figure 2-13 Connecting frequency measurement signals (shown for clock input 0 and external gate 0) .................... 2-25
Figure 2-14 Example of frequency measurement......................................................................................................... 2-26
Figure 2-15 Connecting rate generation sIgnals (shown for counter 0; a software gate is used) ................................. 2-27
Figure 2-16 Example of rate generation mode with a 75% duty cycle........................................................................ 2-28
Figure 2-17 Example of rate generation mode with a 25% duty cycle......................................................................... 2-28
Figure 2-18 Connecting one-shot signals (shown for counter output 0 and gate 0) ..................................................... 2-29
Figure 2-19 Example of one-shot mode using a 99.99% duty cycle ............................................................................ 2-30
Figure 2-20 Example of one-shot mode using a 50% duty cycle ................................................................................. 2-30
Figure 2-21 Example of repetitive one-shot mode using a 99.99% duty cycle ............................................................ 2-31
Figure 2-22 Example of repetitive one-shot mode using a 50% duty cycle ................................................................. 2-32