JYTEK USB-62405, Руководство пользователя

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List of Figures vii
List of Figures
Figure 1-1: U-Test Interface...................................................................7
Figure 1-2: USB-62405 Module Front View ...........................................9
Figure 1-3: USB-62405 Module Side View .............................................9
Figure 1-4: USB-62405 Module Rear View ..........................................10
Figure 1-5: Module, Stand, and USB Cable..........................................11
Figure 1-6: Module, Stand, & Wall Mount Kit Side View (w/ Connections)
12
Figure 1-7: Module In Stand Front View..............................................13
Figure 1-8: Module Stand Top View ....................................................14
Figure 1-9: Module Stand Side Cutaway View.....................................15
Figure 1-10: Module Stand Front View..................................................15
Figure 1-11: BNC Connector Polarity.....................................................16
Figure 2-1: USB-62405 Module in Windows Device Manager.............18
Figure 2-2: Device ID Selection Control ...............................................19
Figure 2-3: Rail Mount Kit....................................................................20
Figure 2-4: Module Pre-Rail Mounting ................................................21
Figure 2-5: Module Rail-Mounted .......................................................22
Figure 2-6: Wall Mount Holes..............................................................23
Figure 2-7: USB-62405 Module with Wall Mount Apparatus..............24
Figure 3-1: USB-62405 Functional Block Diagram ...............................27
Figure 3-2: USB-62405 Analog Front End ............................................28
Figure 3-3: Excitation Current for IEPE Sensor Measurement.............29
Figure 3-4: Input Frequency Response for High Resolution Mode
(Fs=51.2kS/s) .....................................................................32
Figure 3-5: Input Frequency Response for High Speed Mode (Fs=102.4kS/
s) ........................................................................................33
Figure 3-6: Below-Low Analog Triggering............................................34
Figure 3-7: Above-High Analog Triggering...........................................35
Figure 3-8: Digital Triggering ...............................................................35
Figure 3-9: Post Trigger without Retrigger ..........................................36
Figure 3-10: Pre-trigger Mode Operation (valid trigger only) ...............36
Figure 3-11: Pre-trigger Mode Operation (w/ invalid trigger)...............37
Figure 3-12: Delay-Trigger Mode Operation..........................................37
Figure 3-13: Middle-Trigger Acquisition ................................................38
Figure 3-14: Gated Trigger.....................................................................38