JYTEK PXI-62700, Руководство пользователя

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9
3�7 System Reference Clock
The PXI-62700 supplies the PXI 10MHz system clock signal (PXI_CLK10) independently
to every peripheral slot. An independent buffer (having a source impedance matched to
the backplane and a skew of less than 1ns between slots) drives the clock signal to each
peripheral slot. Users can use this common reference clock signal to synchronize multiple
modules in a measurement or control system or drive PXI_CLK10 from an external source
through the PXI_CLK10_IN pin on the P2 connector of the star trigger slot.
Select the internal or external clock by setting the jumper JP1 in the back of the backplane.
JP1: 10MHz Reference Clock
Pin # Name
1-2(default) Internal 10MHz system clock PXI_CLK10
2-3 External clock through the PXI_CLK10_IN
on star trigger slot