JVC XV-BP1B, Руководство по обслуживанию

Страница: 102 / 109

4-21
PIN NO PIN NAME TYPE DESCRIPTION
LDD serial interface (3)
44 LDD_SDIO LDD serial interface data. The pin is spike-free at power-on stage.
45 LDD_CLK LDD serial interface CLK. The pin is spike-free at power-on stage.
46 LDD_SEN
LDD serial interface command enable.
The pin is spike-free at power-on stage.
Panel & sense key (5)
Tray_is_in Input, A Logical Low Indicates the Tray is IN.
67 TRAYIN Feedback Flag is from Tray Connector.
The pin is spike-free at power-on stage.
Tray_is_out Input. A Logical Low Indicates the Tray is OUT.
68 TRAYOUT Feedback Flag is from Tray Connector.
The pin is spike-free at power-on stage.
69 EJECT
Eject/stop key input, active low.
The pin is spike-free at power-on stage.
Sledge Inner Limit Input, Active Low.
72 LIMIT The pin is spike-free at power-on stage.
Alternate function : 1. Internal monitored signal output
73 PLAY
Play/pause key input, active low.
The pin is spike-free at power-on stage.
MISC & GIO function (21)
120 RSTI Analog Input Internal power on reset detection input.
3.3V LVTTL I/O,
62 GIO12
5V-tolerance,
General IO
4,8,12,16mA PDR,
75K pull-up
63 GIO13 General IO.
65 GIO0/MUTE1 General IO
66 GIO1/MUTE2 General IO
LED Control Output. Initial 0 Output.
70 LED1/GIO3 The pin is spike-free at power-on stage.
Alternate function : General I/O
87 GIO4 3.3V LVTTL I/O General IO.
88 GIO5 3.3V LVTTL I/O General IO.
89 GIO6 3.3V LVTTL I/O General IO.
90 GIO7/MUTE3 General IO. The pin is spike-free at power-on stage.
91 GIO8 General IO.
General IO.The pin is spike-free at power-on stage.
92 GIO9/SPOKE The pin is not allowed to pull-up in circuit layout.
Alternate function : Spoke input.
PC RS232 serial receive data.
93
RXD_A/ The pin is spike-free at power-on stage.
LED2/GIO10 Alternate function : 1. LED Control Output. Initial “0” Output
2. General IO.
PC RS232 serial transmit data.
94 TXD_A/GIO11
The pin is spike-free at power-on stage.
Alternate function : 1. LED Control Output. Initial “0” Output
2. General IO.
95 GIO2 General IO
103 GIO14 General IO
104 GIO19 General IO
105 GIO16 General IO
106 GIO17 General IO
107 GIO18 General IO
108 GIO15 General IO The pin is not allowed to pull-up in circuit layout.
Digital Power Pins (11)
60,61,112 DVDD33O Digital Power (3.3V) VDD for digital pad.
109,114 MVDDQ DRAM Power (3.3V) VDD for pad output buffer of DRAM die.
111,113 MVSSQ DRAM Ground VSS for pad output buffer of DRAM die.
59,71,
110,115
DVDD12I Digital Power (1.2V) VDD for internal circuit.
64 VSS Digital Ground VSS for digital pad
3.3V LVTTL I/O,
5V-tolerance,
2,4,6,8mA PDR,
75K pull-up
3.3V LVTTL I/O,
5V-tolerance,
12mA,75K pull-up
3.3V LVTTL I/O,
5V-tolerance,
4,8,12,16mA PDR,
75K pull-down
3.3V LVTTL I/O,
5V-tolerance,
4,8,12,16mA PDR,
75K pull-down