1-17
TH-A30
Name
IRRX1/GPIO0
IDC_CL/GPIO18
IDC_DA/GPIO19
RTS1/GPIO20
RXD1/GPIO21
TXD1/GPIO22
CTS1/GPIO23
RTS2/SPI_CLK/
GPIO37
RXD2/SPI_MISO/
GPIO38
TXD2/SPI_MOSI/
GPIO39
CTS2/SPI_CS/
GPIO40
TRST
TDO
TDI/GPI0
TMS/GPI1
TCK
Pin No.
28
160
161
162
163
164
165
185
186
187
188
197
198
199
200
201
Type
I
I/O
O
I
O
I
O
I
O
I
I
O
I
I
I
Description
IR Remote Receive. This input connects to an integrated (photo diode,
band pass, demodulator) IR receiver. General Purpose I/O 0
Serial clock signal for IDC data transfer. It should be pulled up to the
positive supply voltage, depending on the device) using an external
pull-up resistor. General Purpose I/O [18]
Serial data signal for IDC data transfer. It should be pulled up to the supply
voltage using an external pull-up resistor. General Purpose I/O [19]
Ready to send, UART1
General Purpose I/O [20]
Receive data, UART1
General Purpose I/O [21]
Transmit data, UART1
General Purpose I/O [22]
Clear to send, UART1
General Purpose I/O [23]
Ready to send, UART2
Serial Peripheral Interface Clock
General Purpose I/O [37]
Receive data, UART2
Serial Peripheral Interface - Master Input/Slave Output
General Purpose I/O [38]
Transmit data, UART2
Serial Peripheral Interface - Master Output/Slave Input
General Purpose I/O [39]
Clear to send, UART2
Serial Peripheral Interface ????
General Purpose I/O [40]
Test reset. BST reset - resets the TAP controller.
This signal must be pulled low.
Test data Out. BST serial data output.
Test data In. BST serial data chain input.
General Purpose Input pin 0.
Test mode select. Controls state of test access port (TAP) controller.
General Purpose Input pin 1.
Test clock. Boundary scan test (BST) serial data clock.
IR
IDC
2.
Pin
function
(4/4)
3. Block diagram
UART1
UART2
JTAG
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1
IR
GPIO SPI
UART1&2
ASYNC BUS
IDC
SPARC
Microprocessor
Phase
Lock
Loop
ATAPI
SDRAM Controller
System Control Bus
32-128Mbit
SDRAM
Audio
Output
Unit
JTAG Interface
Track Buffer
Processor
Bus Interface Unit
Audio
Input Unit
Decryption
ZiVA
A/V Core
Graphics
Engine
Interlaced/
Progressive
Video
Encoder
Five 10-bit
Video
DACs
CCIR 656
Digital Video
Composite
Y/R
C
Cr/Pr/G
Cb/Pb/B
Downmix
Left/right
Center/subwoofer
Left/ right/surround
IEC 958/1937
Parallel/serial
DVD Interface
I2S Stereo In
Remote Control
13.5 MHz Crystal
Содержание TH-A30
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