JVC TH-A30, Руководство по обслуживанию

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TH-A30
Name
VNW
VDDP
VDD25
XVDD
VDD
VDD_VDAC[4:0]
VDAC_DVDD
A_VDD[2:1]
VDAC_REFVDD
GNDP
GND
GND25
VDAC_DVSS
AVSS[2:1]
VDAC_REFVSS
XVSS
HCS[4:2]/GPIO[41:43]
HCS[1:0]
HA[3:1]
HA[15:0]
HDTACK/WAIT
HIRQ0
HUDS/UWE
HLDS/LWE
HREAD
ALE
MCS[1:0]
MCAS
MRAS
MDQM[3:0]
MA[11:0]
MD[31:0]
MWE
MCLK
BA[1:0]
HSYNC/HIRQ2/
GPIO1[9]
VCLK
VDATA[7:0]/GPIO[1:7]
VSYNC/HIRQ1/
GPIO36
Pin No.
189
12, 20, 111, 152, 167, 181, 196
32, 44, 55, 63, 74, 87, 98, 104
140
30, 80, 145, 173, 205
118, 121, 124, 127, 130
133
142, 143
134
13, 21, 112, 153, 166, 180, 195, 208
29, 79, 146, 172, 204
31, 43, 54, 61, 72, 85, 96, 103
132
141, 144
136
137
190-192
193, 192
206, 207, 2
3-11, 14-19, 22
23
24
25
26
27
203
50, 49
52
51
97, 86, 73, 62
46, 45, 33-42
102-99, 95-88, 84-81,
78-75, 71-64, 60-57
53
56
47, 48
116
105
106-110, 113-115
184
Type
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
O
I
I/O
I/O
I/OD
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I/O
O
O
O
I/O
I/O
I/O
I/O
Power and Ground
Host Interface
Description
5-V supply voltage for 5V-tolerant I/O signals.
3.3-V supply voltage for I/O signals
3.3-V supply voltage for SDRAM I/O signals
3.3V Crystal interface power
1.8-V supply voltage for core logic
Analog Video DAC Power
3.3V Digital supply for 5 DACs
3.3-V Analog PLL Power
3.3V Analog Video Reference Voltage
Ground for I/O signals
Ground for core logic
Ground for SDRAM I/O signals
Digital VSS for DACs
Analog PLL Ground
Video Analog Ground
Crystal interface ground
Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation. General Purpose I/Os 41, 42, and 43, respectively.
Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation.
Host (muxed address) address bus. 3-bit address bus selects one of eight
host inter-face registers. These signals are not muxed in ATAPI master
mode.
HA[15:0] is the 16-bit (muxed address and data) bi-directional host data
bus through which the host writes data to the decoder Code FIFO. MSB of
the 32-bit word is writ-ten first. The host also reads and writes the decoder
internal registers and local SDRAM/ROM via HA[7:0]. These signals are
not muxed for ATAPI master mode.
Host Data Transfer Acknowledge.
Host interrupt. Open drain signal, must be pulled-up via 4.7k to 3.3 volts.
Driven high for 10 ns before tristate.
Host Upper Data Strobe. Host high byte data, HA[15:8], is valid when this
pin is active.
Host Lower Data Strobe. Host low byte data, HA[7:0], is valid when this pin
is active.
Read/write strobe
Address latch enable
Memory chip select.
Active LOW SDRAM Column Address Strobe.
Active LOW SDRAM Row Address Strobe.
These pins are the bytes masks corresponding to MD[7:0], [15:8], [23:16]
and [31:24]. They allow for byte reads/writes to SDRAM.
SDRAM Address
SDRAM Data
SDRAM Write Enable. Specifies transaction to SDRAM: read (=1) or
write (=0)
SDRAM Clock
SDRAM bank select
Horizontal sync. The decoder begins outputting pixel data for a new
horizontal line after the falling (active) edge of HSYNC.
Host Interrupt Request 2
General Purpose I/O 9
Video clock. Clocks out data on input. VDATA[7:0].
Clock is typically 27 MHz.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At
powerup, the decoder does not drive VDATA. During boot-up, the
decoder uses configuration parameters to drive or 3-state VDATA.
General Purpose I/Os [1:7]
Vertical sync. Bi-directional, the decoder outputs the top border of a new
field on the first HSYNC after the falling edge of VSYNC. VSYNC can
accept vertical synchroni-zation or top/bottom field notification from an
external source. (VSYNC HIGH = bot-tom field. VSYNC LOW = Top field)
Active Low Host Interrupt Pin
General Purpose I/O 36
2. Pin function (2/4)
SDRAM Interface
Digital Video Input/Output
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1