TH-A30
1-14
Name
RESET
VCLK
XOUT
XIN/bypass clk_216
1. Pin layout
2.
Pin
function
(1/4)
ZiVA-5 (U8) : DVD controller
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDD_3.3
VSS
MDATA31
MDATA30
MDATA29
MDATA28
VDD_3.3
MDQM3
VSS
MDATA27
MDATA26
MDATA25
MDATA24
MDATA23
MDATA22
MDATA21
MDATA20
VDD_3.3
MDQM2
VSS
MDATA19
MDATA18
MDATA17
MDATA16
VDDC
VSS
MDATA15
MDATA14
MDATA13
MDATA12
VDD_3.3
MDQM1
VSS
MDATA11
MDATA10
MDATA9
MDATA8
MDATA7
MDATA6
MDATA5
MDATA4
VDD_3.3
MDQM0
VSS
MDATA3
MDATA2
MDATA1
MDATA0
MCLK
VDD_3.3
VSS
MWE
VDD_3.3
HA1
HAD15
HAD14
HAD13
HAD12
HAD11
HAD10
HAD9
HAD8
HAD7
VDD_3.3
VSS
HAD6
HAD5
HAD4
HAD3
HAD2
HAD1
VDD_3.3
VSS
HAD0
HDTACK/
W
A
IT
HIRQ0
UDS/UWE
LDS/LWE
R/W
IRRX1
VSS
VDDC
VSS
VDD_3.3
MADDR9
MADDR8
MADDR7
MADDR6
MADDR5
MADDR4
MADDR3
MADDR2
MADDR1
MADDR0
VSS
VDD_3.3
MADDR10
MADDR11
BA1
BA0
MCS0
MCS1
MRAS
MCAS
DAI-DATA
DAI-BCK/SYSCLKBP
DAI-LRCK/IEC958BP
I
2
C_CL
I
2
C_DA
RTS1
RXD1
TXD1
CTS1
VSS
VDD_3.3
SD-DATA7
SD-DATA6
SD-DATA5
SD-DATA4
VSS
VDDC
SD-DATA3
SD-DATA2
SD-DATA1
SD-DATA0
SD-REQ
SD-EN
VSS
VDD_3.3
SD-ERROR
SD-CLK
VSYNC/HIRQ1
RTS2/SPI_CLK
RXD2/SPI_MISO
TXD2/SPI_MOSI
CTS2/SPI_CS
VDD_5
HCS4
HCS3
HCS2
HCS1
HCS0
VSS
VDD_3.3
TRST
TDO
TDI
TMS
TCK
RESET
ALE
VSS
VDDC
HAD3
HAD2
VSS
DA-IEC958
DA-DATA3
DA-DATA2
VSS
VDD_3.3
DA-DATA1
DA-DATA0
DA-BCK
DA-LRCK
DA-XCK
VSS
VDDC
A_VSS1
A_VDD1
A_VDD2
A_VSS2
XVDD
XTAL/VCLK216BP
XTAL
XVSS
VSS_RREF
VDAC_RREF
VDD_RREF
VDAC_DVDD
VDAC_DVSS
VDAC_0
VDAC_VDD0
VDAC_0B
VDAC_1
VDAC_VDD1
VDAC_1B
VDAC_2
VDAC_VDD2
VDAC_2B
VDAC_3
VDAC_VDD3
VDAC_3B
VDAC_4
VDAC_VDD4
VDAC_4B
HSYNC/
IR
Q
2
VDATA0
VDATA1
VDATA2
VSS
VDD_3.3
VDATA3
VDATA4
VDATA5
VDATA6
VDATA7
VCLK
Pin No.
202
105
138
139
Type
I
I/O
O
I
System Services
Description
Active Low Reset. Assert for at least 5-milliseconds in the presence of
clock to reset the entire chip.
Video clock that outputs 27 MHz.
Crystal output. When the internal DCXO is used, a 13.5 MHz crystal
should be con-nected between this pin and the XIN pin.
Crystal input. When the internal DCXO is used, a 13.5 MHz crystal should
be con-nected between this pin and the XOUT pin. When an external
oscillator or VCXO is used, its output should be connected to this pin.
When configured for an external bypass clock, a 216 MHz clock should be
connected to this pin. The frequency of an external VCXO can be either 27
or 13.5 MHz.
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1
Содержание TH-A30
Страница 29: ...1 29 TH A30 M E M O ...
Страница 38: ...H A B C D E F G 2 6 TH A30 TH A30 oard Switch board Display board d circuit boards ...
Страница 39: ...A B C D E F G 2 7 TH A30 ain board Jack board ...
Страница 40: ...H A B C D E F G 2 8 TH A30 TH A30 ader board Forward side DVD MPEG board Forward side ...
Страница 41: ...A B C D E F G 2 9 TH A30 DVD loader board Reverse side VD MPEG board Reverse side ...
Страница 42: ...H A B C D E F G 2 10 TH A30 TH A30 e side ard d side ...
Страница 43: ...TH A30 M E M O ...
Страница 65: ...TH A30 3 21 M E M O ...