REL 1.0
Page 15 of 53
Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.4
Boot Switches
Cyclone V SoC boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to
begin execution starting from the on-chip boot ROM. The Cyclone V SoC Boot ROM code reads the boot information
register to read the boot select (bsel) and clock select (csel) values to determine the boot source and to set up the
clock manager. The bsel and csel values come from the BOOTSEL and CLKSEL pins which are sampled out of reset.
Cyclone V SoC Qseven SOM supports below mentioned switches for boot purposes which are explained in following
section.
Boot Media Switch
Boot Clock Switch (Optional)
Reset Switch
Figure 3: Boot Switches
